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參數資料
| 型號： | 935276541512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | 7.50 MM, LEAD FREE, PLASTIC, SOT162-1, SO-16 |
| 文件頁數： | 11/34頁 |
| 文件大小： | 251K |
| 代理商： | 935276541512 |
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2003 Jan 27
19
Philips Semiconductors
Product specication
8-bit A/D and D/A converter
PCF8591
14 AC CHARACTERISTICS
All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL and
VIH with an input voltage swing of VSS to VDD.
Note
1. A detailed description of the I2C-bus specification, with applications, is given in brochure
“The I2C-bus and how to
use it”. This brochure may be ordered using the code 9398 393 40011.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
I2C-bus timing (see Fig.20; note 1)
fSCL
SCL clock frequency
100
kHz
tSP
tolerable spike width on bus
100
ns
tBUF
bus free time
4.7
s
tSU;STA
START condition set-up time
4.7
s
tHD;STA
START condition hold time
4.0
s
tLOW
SCL LOW time
4.7
s
tHIGH
SCL HIGH time
4.0
s
tr
SCL and SDA rise time
1.0
s
tf
SCL and SDA fall time
0.3
s
tSU;DAT
data set-up time
250
ns
tHD;DAT
data hold time
0
ns
tVD;DAT
SCL LOW-to-data out valid
3.4
s
tSU;STO
STOP condition set-up time
4.0
s
handbook, full pagewidth
PROTOCOL
SCL
SDA
MBD820
BIT 0
LSB
(R/W)
t HD;STA
t
SU;DAT
t
HD;DAT
t
VD;DAT
t SU;STO
t
f
r
t
BUF
t
SU;STA
t
LOW
t HIGH
1 / f SCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
Fig.20 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
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