
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 13: FGPO: Fast General Purpose Output
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
13-14
3.4.1
Record Synchronization Events
Starting output of sample data for each record is signaled by a output start event
(selected by the FGPO_CTL.REC_SYNC bits):
a rising edge on fgpo_rec_sync pin
a falling edge on fgpo_rec_sync pin
wait FGPO_REC_GAP clock cycles before starting next record, start rst record
immediately
wait for timestamp event
occur immediately after the previous buffer is sent or when output is enabled
The record ends by reaching the programmed record size in the FGPO_REC_SIZE
register or by the next record start event, whichever comes rst.
It takes 4 FGPO clock cycles to synchronize and react to events on the
fgpo_rec_sync pin in external record sync mode. If timestamps are enabled the
output is started on the next FGPO clock tick after the timestamp event.
3.4.2
Buffer Synchronization Events
Each buffer is started by a buffer start event. (selected by the
FGPO_CTL.BUF_SYNC bits):
a rising edge on fgpo_buf_sync pin
a falling edge on fgpo_buf_sync pin
alternating rising and falling edges on fgpo_buf_sync pin, starting with the next
rising edge on fgpo_buf_sync pin
alternating rising and falling edges on fgpo_buf_sync pin, starting with the next
falling edge on fgpo_buf_sync pin
wait FGPO_BUF_SYNC clock cycles before starting next buffer, start rst buffer
immediately
occur immediately after the previous buffer is sent or when output is started
The fgpo_buf_sync signal will only be observed after the current buffer is nished. It
takes 4 FGPO clock cycles to synchronize and react to events on the fgpo_buf_sync
pin in external buffer sync mode.