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參數資料
| 型號： | 93735AF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 93735 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 0.300 INCH, MO-118, SSOP-48 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 155K |
| 代理商： | 93735AF |
ICS93735
IDTTM/ICSTM Low Cost DDR Phase Lock Loop Zero Delay Buffer
ICS93735
REV F 02/11/07
Low Cost DDR Phase Lock Loop Zero Delay Buffer
DATASHEET
Description
Output Features
DDR Zero Delay Clock Buffer
Low skew, low jitter PLL clock driver
I
2C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
3.3V tolerant CLK_INT input
Key Specifications
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz):<110ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
48-pin SSOP package
Available in RoHS compliant packaging
Pin Configuration
Funtional Block Diagram
48-pin SSOP
FB_INT
CLK_INT
PLL
SCLK
SDATA
Control
Logic
FB_OUTT
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
AVDD
CLK_INT
CLKT
CLKC
FB_OUTT
2.5V (nom)
L
H
L
on
2.5V (nom)
H
L
H
on
2.5V (nom)
< offset freq*
offset freq* offset freq* offset freq*
off
GND
L
H
L
Bypassed/off
GND
H
L
H
Bypassed/off
* The offset frequency is ~ 20 MHz, varying somewhat from part to part.
INPUTS
OUTPUTS
PLL State
Funtionality Table
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