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參數資料
| 型號： | 93LC46I/SL |
| 元件分類： | PROM |
| 英文描述： | 128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO14 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-14 |
| 文件頁數： | 6/10頁 |
| 文件大小： | 127K |
| 代理商： | 93LC46I/SL |
1995 Microchip Technology Inc.
DS11168I-page 5
93LC46/56/66
7.0
ERASE ALL
The ERAL instruction will erase the entire memory
array to the logical "1" state. The ERAL cycle is identi-
cal to the ERASE cycle except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the self clocking mode. The ERAL instruction is guar-
anteed at Vcc = +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is com-
plete.
The ERAL cycle takes 15 ms maximum (8 ms typical).
8.0
WRITE ALL
The WRAL instruction will write the entire memory
array with the data specied in the command. The
WRAL cycle is completely self-timed and commences
at the falling edge of the CS. Clocking of the CLK pin
is not necessary after the device has entered the self
clocking mode. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status. The WRAL
instruction is guaranteed at Vcc = +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
The WRAL cycle takes 30 ms maximum (16 ms typi-
cal).
9.0
PIN DESCRIPTION
9.1
Chip Select (CS)
A HIGH level selects the device. A LOW level dese-
lects the device and forces it into standby mode. How-
ever, a programming cycle which is already initiated
and/or in progress will be completed, regardless of the
CS input signal. If CS is brought LOW during a pro-
gram cycle, the device will go into standby mode as
soon as the programming cycle is completed.
CS must be LOW for 250 ns minimum (TCSL) between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
9.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LCXX.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime with respect to clock HIGH time (TCKH)
and clock LOW time (TCKL). This gives the controlling
master freedom in preparing opcode, address, and
data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specied number
of clock cycles (respectively LOW to HIGH transitions
of CLK) must be provided.
These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc-
tion set truth table). CLK and DI then become don't
care inputs waiting for a new start condition to be
detected.
9.3
Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
9.4
Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought HIGH after being LOW for minimum chip select
LOW time (TCSL) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a
pull-up resistor on DO is required to read the READY
signal.
9.5
Organization (ORG)
When ORG is connected to Vcc or oated, the (x16)
memory organization is selected. When ORG is tied to
VSS, the (x8) memory organization is selected. ORG
can only be oated for clock speeds of 1 MHz or less
for the (X16) memory organization. For clock speeds
greater than 1 MHz, ORG must be tied to Vcc or VSS.
Note:
CS must go LOW between consecutive
instructions.
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相關代理商/技術參數 |
參數描述 |
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| 93LC46-ISM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46-ISN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46-P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46-SL | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46-SM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
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