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參數資料
| 型號： | 950201YFLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數： | 1/15頁 |
| 文件大?。?/td> | 204K |
| 代理商： | 950201YFLF-T |
ICS950201
IDTTM Programmable Timing Control HubTM for P4TM
460J—01/25/10
Programmable Timing Control HubTM for P4TM
1
DATASHEET
Pin Configuration
Recommended Application:
CK-408 clock for Intel
845 chipset with P4 processor.
Output Features:
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
Supports spread spectrum modulation,
down spread 0 to -0.5%.
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Uses external 14.318MHz crystal
Stop clocks and functional control available through
I
2C interface.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps, programmable over 800 ps
with groups CPU0,1 and CPU2.
56-Pin SSOP & TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Frequency Table
2
S
F1
S
F0
S
F
U
P
C
)
z
H
M
(
6
V
3
)
z
H
M
(
]
0
:
2
[
f
u
B
6
]
2
:
4
[
6
V
3
)
z
H
M
(
F
_
I
C
P
I
C
P
)
z
H
M
(
00
0
6
.
6
66
6
.
6
66
6
.
6
63
3
.
3
00
1
0
.
0
16
6
.
6
66
6
.
6
63
3
.
3
01
0
.
0
26
6
.
6
66
6
.
6
63
3
.
3
01
1
3
.
3
16
6
.
6
66
6
.
6
63
3
.
3
d
i
M0
0
e
t
a
t
s
i
r
Te
t
a
t
s
i
r
Te
t
a
t
s
i
r
Te
t
a
t
s
i
r
T
d
i
M0
1
2
/
K
L
C
T4
/
K
L
C
T4
/
K
L
C
T8
/
K
L
C
T
d
i
M1
0
d
e
v
r
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s
e
Rd
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v
r
e
s
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Rd
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r
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s
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Rd
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v
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d
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M1
1
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Rd
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