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參數資料
| 型號： | 950211BFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, SSOP-56 |
| 文件頁數： | 1/21頁 |
| 文件大小： | 323K |
| 代理商： | 950211BFT |
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Block Diagram
950211 Rev A 01/23/02
Pin Configuration
Recommended Application:
CK-408 clock with driven mode only for Brookdale chipset with P4
processor.
Output Features:
3 - Pairs of differential CPU clocks (differential current mode)
5 - 3V66 @ 3.3V
10 - PCI @ 3.3V
2 - 48MHz @ 3.3V fixed
1 - REF @ 3.3V, 14.318MHz
1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2C Index read/write and block read/write operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Programmable Timing Control Hub for P4
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
56-Pin 300-mil SSOP
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
Frequency Table
For additional frequency selections please refer to Byte 0.
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_2
3V66_3
3V66_4
3V66_5
#
VDDA
GND
*Vtt_PWRGD#
1
*PD
REF
FS1
FS0
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL0*
I REF
GND
FS2
48MHz_USB/FS3**
48MHz_DOT
VDD48
GND
3V66_1/VCH_CLK/FS4**
PCI_STOP#*
3V66_0
VDD3V66
GND
SCLK
SDATA
1
ICS950211
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PLL2
PLL1
Spread
Spectrum
48MHz_USB
PCICLK (6:0)
3V66 (5:2, 0)
48MHz_DOT
3V66_0/VCH_CLK
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
3V66
DIVDER
WDEN
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
SDATA
SCLK
Vtt_PWRGD#
FS (4:0)
I REF
Control
Logic
Config.
Reg.
REF
3
7
5
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK_F (2:0)
Stop
4
S
F3
S
F2
S
F1
S
F0
S
F
K
L
C
U
P
C
z
H
M
6
V
3
z
H
M
K
L
C
I
C
P
z
H
M
000
0
6
.
6
66
6
.
6
63
3
.
3
000
0
1
0
.
0
16
6
.
6
63
3
.
3
000
1
0
.
0
26
6
.
6
63
3
.
3
000
1
3
.
3
16
6
.
6
63
3
.
3
00
1
0
9
.
0
17
2
.
7
63
6
.
3
00
1
0
1
0
.
5
0
10
0
.
0
70
0
.
5
3
00
1
0
.
9
0
17
6
.
2
73
3
.
6
3
00
1
0
.
4
1
10
0
.
6
70
0
.
8
3
01
0
.
7
1
10
0
.
8
70
0
.
9
3
01
0
1
0
.
7
2
16
8
.
2
73
4
.
6
3
01
0
1
0
.
0
3
19
2
.
4
74
1
.
7
3
01
0
1
0
5
.
2
3
11
7
.
5
79
8
.
7
3
01
1
0
.
5
0
20
0
.
0
70
0
.
5
3
01
1
0
1
0
.
0
7
17
6
.
6
53
3
.
8
2
01
1
0
.
0
8
10
0
.
0
60
0
.
0
3
01
1
0
.
0
9
13
3
.
3
67
6
.
1
3
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change
without notice.
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