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參數資料
| 型號： | 950220AFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件頁數： | 1/22頁 |
| 文件大小： | 201K |
| 代理商： | 950220AFLFT |
Integrated
Circuit
Systems, Inc.
ICS950220
0467F—07/28/05
Block Diagram
Pin Configuration
Recommended Application:
CK-408 clock for Intel
845 chipset.
Output Features:
3 - Pairs of differential CPU clocks @ 3.3V
3 - 3V66 @ 3.3V
9 - PCI @ 3.3V
2 - 48MHz @ 3.3V fixed
1 - 24_48MHz @ 3.3V, 48MHz, 24Mhz or 66MHz
1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Programmable Timing Control Hub for P4
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
48-Pin 300-mil SSOP
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
4
S
F3
S
F2
S
F1
S
F0
S
F
K
L
C
U
P
C
z
H
M
6
V
3
z
H
M
K
L
C
I
C
P
z
H
M
000
0
1
0
.
0
17
6
.
6
63
3
.
3
10
0
1
3
.
3
17
6
.
6
63
3
.
3
111
1
0
7
6
.
6
67
6
.
6
64
3
.
3
111
1
0
.
0
27
6
.
6
63
3
.
3
Frequency Table
For additional frequency selections please refer to Byte 0.
PLL2
PLL1
Spread
Spectrum
48MHz_USB
PCICLK (6:0)
48MHz_DOT
3V66_0/24_48MHZ#
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
WDEN
SEL24_48
MULTSEL0
SDATA
SCLK
Vtt_PWRGD#
PD#
FS (4:0)
I REF
Control
Logic
Config.
Reg.
REF
3
7
3
3V66 (3:1)
3V66
/2
DIVDER
3
CPUCLKT (2:0)
CPUCLKC (2:0)
Reset#
VDDREF
X1
X2
GND
*FS0/PCICLK7
**FS1/PCICLK8
VDDPCI
GND
*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_1
3V66_2
3V66_3
#RESET
VDDA
1
REF/FS2**
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTISEL0*
I REF
GND
48MHz_USB/FS3**
48MHz_DOT/SEL_24_48*
AVDD48
GND
3V66_0/24_48MHZ#/FS4**
VDD3V66
GND
SCLK
SDATA
Vtt_PWRGD/PD#*
GND
1
ICS950220
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
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