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參數資料
| 型號： | 954101YFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 195K |
| 代理商： | 954101YFLFT |
Integrated
Circuit
Systems, Inc.
ICS954101
0815G—12/02/08
Pin Configuration
Recommended Application:
CK410 clock, Intel Yellow Cover part
Output Features:
2 - 0.7V current-mode differential CPU pairs
6 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
1 - 0.7V current-mode differential CPU/SRC selectable
pair
6 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - DOT, 96MHz, 0.7V current differential pair
1 - REF, 14.318MHz
Key Specifications:
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter <125ps
PCI outputs cycle-cycle jitter < 500ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Programmable Timing Control Hub for Desktop P4 Systems
Functionality
Features/Benefits:
Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
Supports spread spectrum modulation, 0 to -0.5%
down spread
Supports CPU clks up to 400MHz
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Supports undriven differential CPU, SRC pair in PD#
for power management.
56-pin SSOP & TSSOP
VDDPCI 1
56 PCICLK2
GND 2
55 PCICLK1
PCICLK3 3
54 PCICLK0
PCICLK4 4
53 FS_C/TEST_SEL
PCICLK5 5
52 REFOUT
GND 6
51 GND
VDDPCI 7
50 X1
ITP_EN/PCICLK_F0 8
49 X2
PCICLK_F1 9
48 VDDREF
PCICLK_F210
47SDATA
VDD4811
46SCLK
USB_48MHz 12
45 GND
GND 13
44 CPUCLKT0
DOTT_96MHz 14
43 CPUCLKC0
DOTC_96MHz 15
42 VDDCPU
FS_B/TEST_MODE 16
41 CPUCLKT1
Vtt_PwrGd#/PD 17
40 CPUCLKC1
FS_A_410 18
39 IREF
SRCCLKT1 19
38 GNDA
SRCCLKC1 20
37 VDDA
VDDSRC 21
36 CPUCLKT2_ITP/SRCCLKT_7
SRCCLKT2 22
35 CPUCLKC2_ITP/SRCCLKC_7
SRCCLKC2 23
34 VDDSRC
SRCCLKT3 24
33 SRCCLKT6
SRCCLKC3 25
32 SRCCLKC6
SRCCLKT4_SATA 26
31 SRCCLKT5
SRCCLKC4_SATA 27
30 SRCCLKC5
VDDSRC 28
29 GND
IC
S95
410
1
FS_C
1
FS_B
2 FS_A2
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
0
266.66
100.00
33.33 14.318
48.00
96.00
0
1
133.33
100.00
33.33 14.318
48.00
96.00
0
1
0
200.00
100.00
33.33 14.318
48.00
96.00
0
1
166.66
100.00
33.33 14.318
48.00
96.00
1
0
333.33
100.00
33.33 14.318
48.00
96.00
1
0
1
100.00
33.33 14.318
48.00
96.00
1
0
400.00
100.00
33.33 14.318
48.00
96.00
1
14.318
48.00
96.00
1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
RESERVED
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