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參數(shù)資料
| 型號(hào)： | 95V157YG-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 0.240 INCH, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 209K |
| 代理商： | 95V157YG-T |
Integrated
Circuit
Systems, Inc.
ICS95V157
0501C—11/24/08
Block Diagram
2.5V Single-Ended to SSTL_2 Clock Driver (45MHz - 233MHz)
Pin Configuration
48-Pin TSSOP
Recommended Application:
Single-ended clock input with zero delay board fan out
Product Description/Features:
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_2)
Feedback pin for input to output synchronization
PD# for power management
Spread Spectrum tolerant inputs
Switching Characteristics:
CYCLE - CYCLE jitter: <60ps
OUTPUT - OUTPUT skew: <60ps
Period jitter: ±30ps
DUTY CYCLE: 49.5% - 50.5%
Functionality
6.10 mm. Body, 0.50 mm. pitch = TSSOP
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