- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25527 > 95VLP857AHLF-T (INTEGRATED DEVICE TECHNOLOGY INC) PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56 PDF資料下載
參數(shù)資料
| 型號： | 95VLP857AHLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56 |
| 封裝： | MO-205, BGA-56 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 116K |
| 代理商： | 95VLP857AHLF-T |
Integrated
Circuit
Systems, Inc.
ICS95VLP8 57
0956B—08/03/04
Block Diagram
2.5V Low Power Wide Range Frequency Clock Driver (45MHz - 233MHz)
Pin Configuration
48-Pin TSSOP/TVSOP
Recommended Application:
DDR Memory Modules / Zero Delay Board Fan Out
Provides complete DDR registered DIMM solution
with ICSSSTVF16857, ICSSSTVF16859 or
ICSSSTV32852
Product Description/Features:
Lower power version than 95VLP857
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
PD# for power management
Spread Spectrum-tolerant inputs
Auto PD when input signal removed
Specifications:
Meets PC3200 Class A+ specification for DDR-I 400
support
Covers all DDRI speed grades
Switching Characteristics:
CYCLE - CYCLE jitter: <50ps
OUTPUT - OUTPUT skew: <40ps
Period jitter: ±30ps
S
T
U
P
N
IS
T
U
P
T
U
O
e
t
a
t
S
L
P
D
V
A#
D
PT
N
I
_
K
L
CC
N
I
_
K
L
CT
K
L
CC
K
L
CT
T
U
O
_
B
FC
T
U
O
_
B
F
D
N
GH
L
H
L
H
L
H
f
o
/
d
e
s
a
p
y
B
D
N
GH
H
L
H
L
H
L
f
o
/
d
e
s
a
p
y
B
V
5
.
2
)
m
o
n
(
LL
H
Z
f
o
V
5
.
2
)
m
o
n
(
LH
LZ
Z
f
o
V
5
.
2
)
m
o
n
(
HL
H
L
H
n
o
V
5
.
2
)
m
o
n
(
HH
L
H
L
H
L
n
o
V
5
.
2
)
m
o
n
(
X)
z
H
M
0
2
<
)
1
(
ZZ
Z
f
o
Functionality
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
PD#
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
6.10 mm Body, 0.50 mm Pitch = TSSOP
4.40 mm Body, 0.40 mm Pitch = TVSOP
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
CLKC2
CLKT2
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
ICS95VLP857
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 95VLP857AKLF-T | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 95VLP857AGLF-T | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9601DM | 96 SERIES, MONOSTABLE MULTIVIBRATOR, CDIP14 |
| 9602DC | 96 SERIES, MONOSTABLE MULTIVIBRATOR, CDIP14 |
| 9601PC | 96 SERIES, MONOSTABLE MULTIVIBRATOR, DIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 95VLP857AKLF | 制造商:Integrated Device Technology Inc 功能描述: |
| 95VLP857AKLFT | 制造商:Integrated Device Technology Inc 功能描述: |
| 95VLP857ALLFT | 功能描述:IC CLK BUF DDR 233MHZ 1CIRC 制造商:idt, integrated device technology inc 系列:- 包裝:帶卷（TR） 零件狀態(tài):過期 PLL:是 主要用途:存儲器，DDR 輸入:LVCMOS 輸出:SSTL-2 電路數(shù):1 比率 - 輸入:輸出:1：10 差分 - 輸入:輸出:是/是 頻率 - 最大值:233MHz 電壓 - 電源:2.3 V ~ 2.7 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.173"，4.40mm 寬） 供應(yīng)商器件封裝:48-TVSOP 標準包裝:1,000 |
| 95VLP857ALT | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Driver Single 45MHz to 233MHz 48-Pin TVSOP T/R 制造商:Integrated Device Technology Inc 功能描述:48 TVSOP - Tape and Reel |
| 95W49-S | 制造商:Leviton Manufacturing Co 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。