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參數資料
| 型號： | 9DB1933AKLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72 |
| 封裝： | ROHS COMPLIANT, PLASTIC, QFN-72 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 174K |
| 代理商： | 9DB1933AKLF |
9DB1933
IDT
Nineteen Output Differential Buffer for PCIe Gen3
1676A—07/12/10
Nineteen Output Differential Buffer for PCIe Gen3
DATASHEET
1
General Description
Output Features
The 9DB1933 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe Gen2
and Gen1. The 9DB1933 is driven by a differential SRC output
pair from an IDT 932S421, 932SQ420, or equivalent, main
clock generator. It attenuates jitter on the input clock and has a
selectable PLL bandwidth to maximize performance in systems
with or without Spread-Spectrum clocking.
19 - 0.7V current mode differential HSCL output pairs
Functional Block Diagram
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew < 150 ps
PCIe Gen3 phase jitter < 1.0ps RMS
Features/Benefits
8 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
11 dedicated and 3 group OE# pins/Hardware control of the
outputs
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible/tracks spreading input clock
for low EMI
SMBus Interface/unused outputs can be disabled
Supports undriven differential outputs in Power Down mode
for power management
Recommended Application
19 output PCIe Gen3 zero-delay/fanout buffer
DIF_IN
DIF_IN#
DIF(18:0)
HIGH_BW#
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CKPWRGD/PD#
19
IREF
OE(17_18)#
OE(15_16)#
OE(14:5)#,
OE_01234#
13
SMB_A0
SMB_A1
PLL
(SS Compatible)
Logic
相關PDF資料 |
PDF描述 |
|---|---|
| 9DB1933AKLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72 |
| 9DB202CGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB202CFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB202CFLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB202CK-01T | 9DB SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 9DB1933AKLFT | 功能描述:時鐘緩沖器 19 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB202CF | 制造商:Integrated Device Technology Inc 功能描述:9DB202CF - Rail/Tube |
| 9DB202CFLF | 功能描述:時鐘合成器/抖動清除器 2 HCSL Output PCIe Buffer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9DB202CFLFT | 功能描述:時鐘緩沖器 2 HCSL Output PCIe Buffer RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB202CFT | 制造商:Integrated Device Technology Inc 功能描述:9DB202CFT - Tape and Reel |
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