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參數資料
| 型號： | 9DB233AGILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 160K |
| 代理商： | 9DB233AGILF |
9DB233
IDT
Two Output Differential Buffer for PCIe Gen3
1667C—04/20/11
Two Output Differential Buffer for PCIe Gen3
1
DATASHEET
Recommended Application:
2 output PCIe Gen3 zero-delay/fanout buffer
General Description:
The 9DB233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB233 is driven by a differential SRC
output pair from an IDT 932S421 or 932SQ420 or equivalent
main clock generator. It attenuates jitter on the input clock
and has a selectable PLL bandwidth to maximize
performance in systems with or without Spread-Spectrum
clocking. An SMBus interface allows control of the PLL
bandwidth and bypass options, while 2 clock request (OE#)
pins make the 9DB233 suitable for Express Card
applications.
Key Specifications:
Cycle-to-cycle jitter < 50 ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
Features/Benefits:
OE# pins/Suitable for Express Card applications
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible/tracks spreading input
clock for low EMI
SMBus Interface/unused outputs can be disabled
Output Features:
2 - 0.7V current mode differential output pairs (HSCL)
Block Diagram
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
SMBDAT
SMBCLK
SRC_IN
SRC_IN#
PLL_BW
IREF
DIF_0
DIF_1
OE1#
OE0#
相關PDF資料 |
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|---|---|
| 9DB233AGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB233AFILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB233AFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB233AFLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB306BFLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 9DB233AGILFT | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB233AGLF | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB233AGLFT | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB306BF | 制造商:Integrated Device Technology Inc 功能描述:9DB306BF - Rail/Tube |
| 9DB306BFT | 制造商:Integrated Device Technology Inc 功能描述:9DB306BFT - Tape and Reel |
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