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參數資料
| 型號： | 9FG1901YKLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-220, MLF-72 |
| 文件頁數： | 1/17頁 |
| 文件大?。?/td> | 233K |
| 代理商： | 9FG1901YKLF-T |
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
Recommended Application:
DB1900G: CPU Host Bus, PCI Express and Fully-Buffered
DIMM clocking
Features:
Power up default is all outputs in 1:1 mode
DIF_(16:0) can be “gear-shifted” from the input CPU
Host Clock
DIF_(18:17) can be “gear-shifted” from the input CPU
Host Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
VDDA controlled power down mode
Key Specifications:
DIF output cycle-to-cycle jitter < 50ps
DIF (0:18) output-to-output skew < 225ps
DIF (0:16) output-to-output skew < 100ps
Frequency Generator for P4
CPU, PCI Express & Fully Buffered DIMM Clocks
Other names and brands may be claimed as the property of others.
Power Down Functionality
Pin Configuration
72-pin MLF
Functionality at Power Up (PLL Mode)
SM
B
_
A
2
_
P
L
BY
P#
CL
K
_
IN
#
CL
K
_
IN
O
E
17
_1
8#
DI
F
_
1
8
#
DI
F
_
1
8
DI
F
_
1
7
#
DI
F
_
1
7
GND
VD
D
DI
F
_
1
6
#
DI
F
_
1
6
OE
1
6
#
DI
F
_
1
5
#
DI
F
_
1
5
OE
1
5
#
DI
F
_
1
4
#
DI
F
_
1
4
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
IREF
1
54 OE14#
GNDA
2
53 DIF_13#
VDDA/PD#
3
52 DIF_13
HIGH_BW#
4
51 OE13#
FS_A_410
5
50 DIF_12#
DIF_0
6
49 DIF_12
DIF_0#
7
48 OE12#
DIF_1
8
47 VDD
DIF_1#
9
46 GND
GND 10
45 DIF_11#
VDD 11
44 DIF_11
DIF_2 12
43 OE11#
DIF_2# 13
42 DIF_10#
DIF_3 14
41 DIF_10
DIF_3# 15
40 OE10#
DIF_4 16
39 DIF_9#
DIF_4# 17
38 DIF_9
OE_01234# 18
37 OE9#
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SM
B
C
L
K
SM
B
D
AT
OE
5
#
DI
F
_
5
DI
F
_
5
#
OE
6
#
DI
F
_
6
DI
F
_
6
#
VD
D
GN
D
OE
7
#
DI
F
_
7
DI
F
_
7
#
OE
8
#
DI
F
_
8
DI
F
_
8
#
S
M
B_
A0
S
M
B_
A1
ICS9FG1901
FS_A_410
1
CLK_IN (CPU FSB)
MHz
DIF_(18:0)
MHz
1
100 <= CLK_IN < 200
CLK_IN
0
200<= CLK_IN <= 400
CLK_IN
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for
correct values.
VDDA/PD#
CLK_IN/CLK_IN#
DIF
DIF#
3.3V (NOM)
Running
ON
GND
X
OFF
Functionality Note
It is recommended that Byte 2, bit 6 be toggled from 1 to 0
and back to 1, the first time VDDA is applied. This ensures
proper initialization of the device.
Hi-Z
INPUTS
OUTPUTS
PLL State
Running
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 9FG1902AKLF | 制造商:Integrated Device Technology Inc 功能描述:PCIE BUFFER 制造商:Integrated Device Technology Inc 功能描述:72 VFQFN (LEAD FREE) - Rail/Tube |
| 9FG1902AKLFT | 制造商:Integrated Device Technology Inc 功能描述:PCIE BUFFER 制造商:Integrated Device Technology Inc 功能描述:72 VFQFN (LEAD FREE) - Tape and Reel |
| 9FG1903AK-1LF | 制造商:Integrated Device Technology Inc 功能描述:PCIE BUFFER 制造商:Integrated Device Technology Inc 功能描述:72 VFQFN (LEAD FREE) - Rail/Tube |
| 9FG1903AK-1LFT | 功能描述:時鐘緩沖器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9FG1903AKLF | 功能描述:時鐘緩沖器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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