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參數資料
型號: 9LPRS480YKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, PQCC64
封裝: ROHS COMPLIANT, PLASTIC, MLF-64
文件頁數: 1/25頁
文件大小: 249K
代理商: 9LPRS480YKLFT
Integrated
Circuit
Systems, Inc.
ICS9LPRS480
1391D—02/02/09
Pin Configuration
Recommended Application:
ATI RS780 systems using AMD K8 processors
Output Features:
Integrated series resistors on all differential outputs.
1 - Greyhound compatible K8 CPU pairs
5 - low-power differential SRC pairs
2 - low-power differential chipset SouthBridge SRC pairs
1 - Selectable low-power differential 100MHz non-spread
SATA/ SRC output
1 - Selectable low-power differential SRC / 27MHz Single
Ended outputs
1 - Selectable HT3 100MHz low-power differential
hypertransport clock / HT66MHz Single Ended outputs
1 - 48MHz USB clock
3 - 14.318MHz Reference clock
2 - low-power differential ATIG pairs
5- Dedicated CLKREQ# pins
Programmable System Clock Chip for ATI RS780 - K8
TM based Systems
*Other names and brands may be claimed as the property of others.
Key Specifications:
CPU outputs cycle-to-cycle jitter < 150ps
SRC outputs cycle-to-cycle jitter < 125ps
SB_SRC outputs cycle-to-cycle jitter < 125ps
+/- 100ppm frequency accuracy on CPU, SRC, ATIG
0ppm frequency accuracy on 48MHz
Features/Benefits:
Power Saving Features:
Optional Separate supply rail for SRC low Voltage I/O
- ~33% power saving when 1.5V is used for this rail
Spread Spectrum for EMI reduction
Outputs may be disabled via SMBus
External crystal load capacitors for maximum
frequency accuracy
48M
H
z
_0
V
DD4
8
X2
X1
GN
DR
E
F
R
E
F0
/S
E
L
_
H
TT6
6
R
E
F
1
/SEL
_
SAT
A
R
E
F
2
/SEL
_
2
7
V
DDR
E
F
V
DDH
T
H
T
0
T
_LP
R
S
/66M
H
T
0
C
_LP
R
S
/66M
GN
DH
T
PD
#
CP
UK
G
0
T
_
L
P
RS
CP
UK
G
0
C
_
L
P
RS
64 63
62
61
60 59 58
57
56
55
54
53
52
51
50
49
GND48 1
48 VDDCPU
SMBCLK 2
47 VDDCPU_IO
SMBDAT 3
46 GNDCPU
VDD 4
45 CLKREQ1#*
SRC7C_LPRS/27MHz_NS 5
44 CLKREQ2#*
SRC7T_LPRS/27MHz_SS 6
43 GNDSATA
GND 7
42 SRC6T/SATAT_LPRS
SRC4C_LPRS 8
41 SRC6C/SATAC_LPRS
SRC4T_LPRS 9
40 VDDSATA
GNDSRC 10
39 CLKREQ3#*
VDDSRC_IO 11
38 CLKREQ4#*
SRC3C_LPRS 12
37 SB_SRC0T_LPRS
SRC3T_LPRS 13
36 SB_SRC0C_LPRS
SRC2C_LPRS 14
35 VDDSB_SRC
SRC2T_LPRS 15
34 VDDSB_SRC_IO
VDDSRC 16
33 GNDSB_SRC
17 18
19
20
21 22 23
24
25
26
27
28
29
30
31
32
V
D
DS
RC
_
IO
GND
S
RC
S
R
C1C
_LP
R
S
R
C1T
_LP
R
S
R
C0C
_LP
R
S
R
C0T
_LP
R
S
*C
L
K
R
E
Q0
#
G
NDA
T
IG
V
DDA
T
IG
_
IO
V
DDA
T
IG
A
T
IG
1C
_LP
RS
A
T
IG
1T
_LP
R
S
A
T
IG
0C
_LP
RS
A
T
IG
0T
_LP
R
S
B
_S
R
C
1C
_LP
RS
S
B
_S
R
C
1T
_LP
RS
ICS9LPRS480
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