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參數資料
| 型號： | 9LRS4103BKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC32 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-32 |
| 文件頁數： | 12/15頁 |
| 文件大?。?/td> | 188K |
| 代理商： | 9LRS4103BKLFT |
IDT PC MAIN CLOCK
1520D—01/06/11
ICS9LRS4103
PC MAIN CLOCK
6
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
0
ppm
1,6
Clock period
Tperiod
14.318180 MHz output nominal
69.8413
ns
6
Absolute min/max period
Tabs
14.318180 MHz including cycle to cycle
jitter
68.8413
69.8413
70.84128
ns
6
Output High Voltage
VOH
IOH = -1 mA
2.4
3
V
1
Output Low Voltage
VOL
IOL = 1 mA
0.2
0.4
V
1
Output High Current
IOH
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
-33
mA
1
Output Low Current
IOL
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
30
38
mA
1
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
2.5
4
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
2.5
4
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
52
55
%
1
Jitter
tjcyc-cyc
VT = 1.5 V
100
1000
ps
1
Electrical Characteristics - SMBus Interface
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
SMBus Voltage
VDD
2.7
3.3
5.5
V
1
Low-level Output Voltage
VOLSMB
@ IPULLUP
0.3
0.4
V
1
Current sinking at
VOLSMB = 0.4 V
IPULLUP
SMB Data Pin
4
mA
1
SCLK/SDATA
Clock/Data Rise Time
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
Maximum SMBus
Operating Frequency
FSMBUS
Block Mode
400
100
kHz
1
Notes on Electrical Characteristics:
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF has been tuned to exactly 14.318180 MHz
8 Maximum input voltage is not to exceed maximum VDD
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is
measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage
thresholds the oscilloscope is to use for the edge rate calculations.
7 Operation under these conditions is neither implied, nor guaranteed.
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