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參數資料
| 型號： | A1186LUA-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數： | 13/15頁 |
| 文件大?。?/td> | 509K |
| 描述： | IC SWITCH HALL EFFECT UNI 3-SIP |
| 產品培訓模塊： | Current Sensor |
| 標準包裝： | 500 |
| 傳感范圍： | 10G ~ 60G 跳閘 - 可編程，固定釋放 |
| 類型： | 單極開關 |
| 電源電壓： | 3.5 V ~ 24 V |
| 電流 - 電源： | 6.9mA |
| 輸出類型： | 數字，開路集電極 |
| 特點： | 可編程 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 3-SIP |
| 供應商設備封裝： | 3-SIP |
| 包裝： | 散裝 |
Ultrasensitive Two-Wire Field-Programmable
Chopper-Stabilized Unipolar Hall Effect Switches
A1185 and
A1186
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
V
PH
V+
t
V
PM
V
PL
0
Address 1
Address 2
Address n ( d 127)
Figure 8. Pulse sequence to select addresses
Falling edge of final B
OP
address digit
V
PH
V+
t
V
PM
V
PL
0
Encode Lock Bit
Enable
Address
Blow
128 pulses
Figure 9. Pulse sequence to encode lock bit
Lock Bit Programming. After the desired B
OP
calibration value
is programmed, and all of the corresponding bitfield-level fuses
are blown, the device-level fuse should be blown. To do so, the
lock bit (bitfield address 32) should be encoded as 1 and have
its fuse blown. This is done in the same manner as permanently
setting the other bitfields, as shown in figure 9.
Enabling Addressing Mode. The first segment of code is a
keying sequence used to enable the bitfield addressing mode. As
shown in figure 7, this segment consists of one short V
PH
pulse,
one V
PM
pulse, and one short V
PH
pulse, with no supply inter-
ruptions. This sequence is designed to prevent the device from
being programmed accidentally, such as by noise on the supply
line.
Figure 7. Addressing mode enable pulse sequence
V
PH
V+
t
V
PM
V
PL
0
Address Selection. After addressing mode is enabled, the
target bitfield address, is indicated by a series of V
PM
pulses, as
shown in figure 8.
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