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參數資料
| 型號： | A32400DX-BG313C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2526 CLBS, 40000 GATES, PBGA313 |
| 封裝： | BGA-313 |
| 文件頁數： | 1/22頁 |
| 文件大小： | 217K |
| 代理商： | A32400DX-BG313C |
August 1995
1
1995 Actel Corporation
Preliminary
3200DX Field Programmable Gate Arrays
– The System Logic Integrator Family
Features
High Capacity
Up to 40,000 logic gates
Up to 4 Kbits dual-port SRAM
Fast wide decode circuitry
Up to 292 User-programmable I/O Pins
High Performance
200 MHz datapath applications
5 ns Dual-Port SRAM
100 MHz FIFOs
7.5 ns 35-bit Address Decode
Ease-of-Integration
JTAG 1149.1 Boundary Scan Testing
Synthesis-friendly architecture supports ASIC design
methodologies
95–100% logic utilization using automatic Place and
Route Tools
Deterministic, user-controllable timing via
DirectTime software tools
Designer Series development tool support including
interfaces to popular design environments such as
Cadence, Escalade, Exemplar Logic, IST, Mentor
Graphics, Synopsys and Viewlogic
Pin compatible with 1200XL Family
General Description
The 3200DX, the first device family in Actel’s Integrator
Series, are the first FPGAs optimized for high-speed,
high-complexity system logic integration. Based on Actel’s
proprietary PLICE antifuse technology and state-of-the-art
0.6-micron double metal CMOS process, the 3200DX offers
a fine-grained, register-rich architecture with the industry’s
fastest embedded dual-port SRAM.
The 3200DX was designed to integrate high performance
system logic functions typically implemented in multiple
CPLDs, PALs, and FPGAs. The 3200DX is the first
programmable logic device to embed dual-port SRAM into
the programmable array. Offering 5 ns access time, the
3200DX provides the fastest embedded SRAM of any
programmable logic device on the market today. This
combination of fast, flexible SRAM blocks with a true
dual-port architecture, allows designers to implement
extremely fast SRAM functions such as FIFOs, LIFOs and
scratchpad memory. The large number of storage elements
can efficiently address applications requiring wide datapath
manipulation
and
transformation
functions
such
as
telecommunications, networking, DSP and bus interfaces.
The control and decode functions typically implemented in
CPLDs can easily be integrated into the 3200DX by taking
advantage of the wide decode modules.
The 3200DX family is supported by Actel’s Designer Series
3.0 software which provides a seamless integration into any
ASIC design flow.
The Designer Series development tools
offer automatic or fixed pin assignments, automatic
placement and routing (with optional manual placement),
Product Family Profile
Device
A3265DX
A32100DX
A32140DX
A32200DX
A32300DX
A32400DX
Capacity
Logic Gates
Dual-Port SRAM Bits
6,500
N/A
10,000
2,048
14,000
N/A
20,000
2,560
30,000
3,072
40,000
4,096
Logic Modules
Sequential
Combinatorial
Decode
510
475
20
700
662
20
954
912
24
1,230
1,184
24
1,888
1,833
28
2,526
2,466
28
SRAM Modules (64x4 or 32x8)
N/A
8
N/A
10
12
16
Clocks
262666
JTAG
No
Yes
User I/O
126
156
176
206
254
292
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