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參數(shù)資料
型號(hào): A3PN125-Z1VQG100
元件分類: FPGA
英文描述: FPGA, 3072 CLBS, 125000 GATES, PQFP100
封裝: 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100
文件頁數(shù): 12/100頁
文件大小: 3284K
代理商: A3PN125-Z1VQG100
ProASIC3 nano DC and Switching Characteristics
Ad vance v0.2
2-5
Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software refers to the junction temperature, not
the ambient temperature. This is an important distinction because dynamic and static power
consumption cause the chip junction to be higher than the ambient temperature.
EQ 2-1 can be used to calculate junction temperature.
TJ = Junction Temperature = ΔT + TA
EQ 2-1
where:
TA = Ambient Temperature
ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θ
ja * P
θ
ja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is
θ
jc and the junction-to-ambient air thermal
resistivity is
θ
ja. The thermal characteristics for θja are shown for two air flow rates. The absolute
maximum junction temperature is 100°C. EQ 2-2 shows a sample calculation of the absolute
maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and
in still air.
EQ 2-2
Temperature and Voltage Derating Factors
Maximum Power Allowed
Max. junction temp. (
°C) Max. ambient temp. (°C)
θ
ja(°C/W)
---------------------------------------------------------------------------------------------------------------------------------------
100
°C70°C
20.5
°C/W
------------------------------------
1.463 W
=
Table 2-5
Package Thermal Resistivities
Package Type
Device
Pin Count
θ
jc
θ
ja
Units
Still Air 200 ft./min. 500 ft./min.
Quad Flat No Lead (QFN)
All devices
48
TBD
C/W
68
TBD
C/W
100
TBD
C/W
Very Thin Quad Flat Pack (VQFP)
All devices
100
10.0
35.3
29.4
27.1
C/W
Table 2-6
Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ = 70°C, VCC = 1.425 V)
Array Voltage VCC (V)
Junction Temperature (°C)
–40°C
–20°C
0°C
25°C
70°C
85°C
110°C
1.425
0.968
0.973
0.979
0.991
1.000
1.006
1.013
1.500
0.888
0.894
0.899
0.910
0.919
0.924
0.930
1.575
0.836
0.841
0.845
0.856
0.864
0.870
0.875
相關(guān)PDF資料
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A3PN125-Z1VQG100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)
A3PN125-Z2VQ100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)
A3PN125-Z2VQ100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)
A3PN125-Z2VQG100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)
A3PN125-Z2VQG100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)
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