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參數資料
型號: A40MX04-1PL44MX79
元件分類: FPGA
英文描述: FPGA, 547 CLBS, 6000 GATES, 92 MHz, PQCC44
封裝: PLASTIC, LCC-44
文件頁數: 95/124頁
文件大小: 3142K
代理商: A40MX04-1PL44MX79
40MX and 42MX FPGA Families
1- 66
v6.1
Table 37
A42MX24 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
2.0
1.8
2.1
2.5
3.4
ns
tPDD
Internal Decode Module Delay
1.1
2.2
2.5
3.0
4.2
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.7
1.3
1.4
1.7
2.3
ns
tRD2
FO=2 Routing Delay
2.0
1.6
1.8
2.1
3.0
ns
tRD3
FO=3 Routing Delay
1.1
2.0
2.2
2.6
3.7
ns
tRD4
FO=4 Routing Delay
1.5
2.3
2.6
3.1
4.3
ns
tRD5
FO=8 Routing Delay
1.8
3.7
4.2
5.0
7.0
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
2.1
2.0
2.3
2.7
3.7
ns
tGO
Latch Gate-to-Output
3.4
1.9
2.1
2.5
3.4
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
2.0
2.2
2.5
2.9
4.1
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.7
0.8
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.6
5.2
5.8
6.9
9.6
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.1
6.8
7.7
9.0
12.6
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.4
1.6
1.8
2.2
3.0
ns
tINGO
Input Latch Gate-to-
Output
1.8
1.9
2.2
2.6
3.6
ns
tINH
Input Latch Hold
0.0
ns
tINSU
Input Latch Set-Up
0.7
0.8
1.0
1.4
ns
tILA
Latch Active Pulse Width
6.5
7.3
8.2
9.7
13.5
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關PDF資料
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A40MX04-1PL44M FPGA, 547 CLBS, 6000 GATES, 92 MHz, PQCC44
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相關代理商/技術參數
參數描述
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