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參數(shù)資料
型號: A40MX04-FPL44
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 1/116頁
文件大小: 3110K
代理商: A40MX04-FPL44
February 2001
2001 Actel Corporation
1
v5.0
40MX and 42MX FPGA Families
Features
High Capacity
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
High Performance
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
HiRel Features
Commercial, Industrial, and Military Temperature Plastic
Packages
Commercial, Military Temperature and MIL-STD-883
Ceramic Packages
QML Certification
Ceramic Devices Available to DSCC SMD
Ease of Integration
Mixed Voltage Operation (5.0V or 3.3V I/O)
Synthesis-Friendly Architecture to Support ASIC Design
Methodologies
Up to 100% Resource Utilization and 100% Pin Fixing
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
5.0V and 3.3V Programmable PCI-Compliant I/O
Product Profile
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Capacity
System Gates
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
Clock-to-Out
3,000
N/A
6,000
N/A
14,000
N/A
24,000
N/A
36,000
N/A
54,000
2,560
295
9.5 ns
547
9.5 ns
348
336
N/A
5.6 ns
624
608
N/A
6.1 ns
954
912
24
6.1 ns
1,230
1,184
24
6.3 ns
SRAM Modules
(64x4 or 32x8)
N/A
147
1
57
No
No
N/A
273
1
69
No
No
N/A
348
516
2
104
No
No
N/A
624
928
2
140
No
No
N/A
954
1,410
2
176
Yes
Yes
10
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
User I/O
(Maximum)
PCI
Boundary Scan Test (BST)
Packages
(by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
1,230
1,822
6
202
Yes
Yes
44, 68
100
80
44, 68, 84
100
80
84
100, 160
100
176
84
100, 160, 208
100
176
84
160, 208
176
208, 240
208, 256
272
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