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參數資料
型號: A40MX04-PL84A
元件分類: FPGA
英文描述: FPGA, 547 CLBS, 6000 GATES, 116 MHz, PQCC84
封裝: PLASTIC, LCC-84
文件頁數: 93/124頁
文件大小: 3142K
代理商: A40MX04-PL84A
40MX and 42MX FPGA Families
1- 64
v6.1
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
2.4
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.8
3.2
3.6
4.2
5.9
ns
tENZH
Enable Pad Z to HIGH
2.5
2.8
3.2
3.8
5.3
ns
tENZL
Enable Pad Z to LOW
2.8
3.1
3.5
4.2
5.9
ns
tENHZ
Enable Pad HIGH to Z
5.2
5.7
6.5
7.6
10.7
ns
tENLZ
Enable Pad LOW to Z
4.8
5.3
6.0
7.1
9.9
ns
tGLH
G-to-Pad HIGH
2.9
3.2
3.6
4.3
6.0
ns
tGHL
G-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tLSU
I/O Latch Output Set-Up
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Output Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.6
6.1
6.9
8.1
11.4
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.6
11.8
13.4
15.7
22.0
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.05
0.07
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.03
0.04
0.06
ns/pF
Table 36
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關PDF資料
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A40MX04-PL84IX79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC84
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相關代理商/技術參數
參數描述
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A40MX04-PLG44 功能描述:IC FPGA 69I/O 44PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:MX 標準包裝:24 系列:ECP2 LAB/CLB數:1500 邏輯元件/單元數:12000 RAM 位總計:226304 輸入/輸出數:131 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP(28x28)
A40MX04-PLG44I 功能描述:IC FPGA MX SGL CHIP 6K 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數:- 邏輯元件/單元數:- RAM 位總計:36864 輸入/輸出數:157 門數:250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA(17x17)
A40MX04-PLG44M 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 44PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 34 I/O 44PLCC
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