- 您現在的位置：買賣IC網 > PDF目錄298742 > A42MX02-2PQ100ES (Electronic Theatre Controls, Inc.) 40MX and 42MX FPGA Families PDF資料下載
參數資料
| 型號： | A42MX02-2PQ100ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數： | 1/53頁 |
| 文件大小： | 854K |
| 代理商： | A42MX02-2PQ100ES |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
January 2004
i
2004 Actel Corporation
See the Actel website (www.actel.com) for the latest version of this datasheet.
40MX and 42MX FPGA Families
Features
High Capacity
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
High Performance
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
HiRel Features
Commercial, Industrial, Automotive, and Military
Temperature Plastic Packages
Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
QML Certification
Ceramic Devices Available to DSCC SMD
Ease of Integration
Mixed-Voltage Operation (5.0V or 3.3V for core and
I/Os), with PCI-Compliant I/Os
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique
In-System
Diagnostic
and
Verification
Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Capacity
System Gates
SRAM Bits
3,000
–
6,000
–
14,000
–
24,000
–
36,000
–
54,000
2,560
Logic Modules
Sequential
Combinatorial
Decode
–
295
–
547
–
348
336
–
624
608
–
954
912
24
1,230
1,184
24
Clock-to-Out
9.5 ns
5.6 ns
6.1 ns
6.3 ns
SRAM Modules
(64x4 or 32x8)
–––
–
10
Dedicated Flip-Flops
–
348
624
954
1,230
Maximum Flip-Flops
147
273
516
928
1,410
1,822
Clocks
11
2
6
User I/O (maximum)
57
69
104
140
176
202
PCI
–––
–
Yes
Boundary Scan Test (BST)
–––
–
Yes
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
44, 68
100
80
–
44, 68, 84
100
80
–
84
100, 160
100
176
–
84
100, 160, 208
100
176
–
84
160, 208
–
176
–
208, 240
–
208, 256
272
v6.0
相關PDF資料 |
PDF描述 |
|---|---|
| A42MX02-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX02-2TQ100A | 40MX and 42MX FPGA Families |
| A42MX02-2TQ100B | 40MX and 42MX FPGA Families |
| A42MX02-2TQ100ES | 40MX and 42MX FPGA Families |
| A42MX02-2VQ100 | 40MX and 42MX FPGA Families |
相關代理商/技術參數 |
參數描述 |
|---|---|
| A42MX02-2PQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX02-2PQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX02-2TQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX02-2TQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX02-2TQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
發布緊急采購，3分鐘左右您將得到回復。