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參數(shù)資料
| 型號(hào)： | A6B595KLWTR-T |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 0.5 A LATCH BASED PRPHL DRVR, PDSO20 |
| 封裝： | LEAD FREE, PLASTIC, MS-013AC, SOICW-20 |
| 文件頁(yè)數(shù)： | 10/10頁(yè) |
| 文件大小： | 337K |
| 代理商： | A6B595KLWTR-T |
8-Bit Serial-Input DMOS Power Driver
A6B595
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package A, 18-Pin DIP
Package LW, 20-Pin SOICW
5.33 MAX
0.46 ±0.12
22.86 ±0.51
6.35 +0.76
–0.25
3.30 +0.51
–0.38
10.92 +0.38
–0.25
1.52 +0.25
–0.38
7.62
2.54
0.25 +0.10
–0.05
C
SEATING
PLANE
2
1
18
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
All dimensions nominal, not for tooling use
(reference JEDEC MS-001 AC)
Dimensions in inches
2
1
20
2
1
20
A
2.65 MAX
C
SEATING
PLANE
C
0.10
20X
A Terminal #1 mark area
GAUGE PLANE
SEATING PLANE
B
2.25
0.65
9.50
1.27
PCB Layout Reference View
For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
B Reference pad layout (reference IPC SOIC127P1030X265-20M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
1.27
0.25
0.20 ±0.10
0.41 ±0.10
12.80±0.20
10.30±0.33
7.50±0.10
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
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