
2002
Document No. D16159EJ1V0DS00 (1st edition)
Date Published April 2002 N CP(K)
Printed in Japan
COMPOUND TRANSISTOR
AA1A3Q
on-chip resistor NPN silicon epitaxial transistor
For mid-speed switching
DATA SHEET
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
FEATURES
On-chip bias resistor
(R
1
= 1.0 k
, R
2
= 10 k
)
Complementary transistor with AN1A3Q
ABSOLUTE MAXIMUM RATINGS (Ta = 25
°
C)
Parameter
Symbol
Ratings
Unit
Collector to base voltage
V
CBO
60
V
Collector to emitter voltage
V
CEO
50
V
Emitter to base voltage
V
EBO
5
V
Collector current (DC)
I
C(DC)
100
mA
Collector current (Pulse)
I
C(pulse)
*
200
mA
Total power dissipation
P
T
250
mW
Junction temperature
T
j
150
°
C
Storage temperature
T
stg
55 to +150
°
C
* PW
≤
10 ms, duty cycle
≤
50 %
PACKAGE DRAWING (UNIT: mm)
ELECTRICAL CHARACTERISTICS (Ta = 25
°
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Collector cutoff current
I
CBO
V
CB
= 50 V, I
E
= 0
100
nA
DC current gain
h
FE1
**
V
CE
= 5.0 V, I
C
= 5.0 mA
35
60
100
DC current gain
h
FE2
**
V
CE
= 5.0 V, I
C
= 50 mA
80
230
Collector saturation voltage
V
CE(sat)
**
I
C
= 5.0 mA, I
B
= 0.25 mA
0.05
0.2
V
Low level input voltage
V
IL
**
V
CE
= 5.0 V, I
C
= 100
μ
A
0.7
0.9
V
High level input voltage
V
IH
**
V
CE
= 0.2 V, I
C
= 5.0 mA
2.0
1.0
V
Input resistance
R
1
0.7
1.0
1.3
k
E-to-B resistance
R
2
7
10
13
k
Turn-on time
t
on
0.2
μ
s
Storage time
t
stg
5.0
μ
s
Turn-off time
t
off
V
CC
= 5 V, R
L
= 1 k
V
I
= 5 V, PW = 2
μ
s
duty cycle
≤
2 %
6.0
μ
s
**PW
≤
350
μ
s, duty cycle
≤
2 %