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參數資料
| 型號： | AC109M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET |
| 中文描述： | 雙JK上升沿觸發器，沒有明確的和預置觸發器 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 355K |
| 代理商： | AC109M |
CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
±
24-mA Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The ’AC109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and
is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs
can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E
Tube
CD74AC109E
CD74AC109E
–55
°
C to 125
°
C
SOIC – M
CDIP – F
Tape and reel
Tube
CD74AC109M96
CD54AC109F3A
AC109M
CD54AC109F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
CD54AC109 . . . F PACKAGE
CD74AC109 . . . E OR M PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1CLR
1J
1K
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2J
2K
2CLK
2PRE
2Q
2Q
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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