
SCAS521F AUGUST 1995 REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2-V to 6-V V
CC
Operation
Inputs Accept Voltages to 6 V
Max t
pd
of 10 ns at 5 V
description/ordering information
The ’AC74 devices are dual positive-edge-
triggered D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at D can be changed without affecting the levels
at the outputs.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74AC74N
SN74AC74N
SOIC D
Tube
SN74AC74D
AC74
Tape and reel
SN74AC74DR
°
C to 85
°
C
40
SOP NS
Tape and reel
SN74AC74NSR
AC74
SSOP DB
Tape and reel
SN74AC74DBR
AC74
TSSOP PW
Tube
SN74AC74PW
AC74
Tape and reel
SN74AC74PWR
CDIP J
Tube
SNJ54AC74J
SNJ54AC74J
55 C to 125 C
CFP W
Tube
SNJ54AC74W
SNJ54AC74W
LCCC FK
Tube
SNJ54AC74FK
SNJ54AC74FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54AC74 . . . FK PACKAGE
(TOP VIEW)
SN54AC74 . . . J OR W PACKAGE
SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1
1
N
2
2
C
2
1
G
N
NC No internal connection
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