
Features
eroflex Circuit Technology – RISC TurboEngines For The Future SCD5260 REV 3 12/22/98
BLOCK DIAGRAM
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Full militarized QED RM5260 microprocessor
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Dual Issue superscalar QED RISCMark
- can issue one
integer and one floating-point instruction per cycle
microprocessor - can issue one integer and one
floating-point instruction per cycle
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100, 133 and 150MHz frequency (200MHz future option)
Consult Factory for latest speeds
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260 Dhrystone2.1 MIPS
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SPECInt95 4.8. SPECfp95 5.1
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High performance system interface compatible with R4600,
R4700 and R5000
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64-bit multiplexed system address/data bus for optimum
price/performance up to 100 MHz operating frequency
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High performance write protocols maximize uncached
write bandwidth
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Operates at input system clock multipliers of 2 through 8
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5V tolerant I/O's
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IEEE 1149.1 JTAG boundary scan
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Integrated on-chip caches - up to 3.2GBps internal data rate
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16KB instruction - 2 way set associative
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16KB data - 2 way set associative
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Virtually indexed, physically tagged
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Write-back and write-through on per page basis
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Pipeline restart on first double for data cache misses
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Integrated memory management unit
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Fully associative joint TLB (shared by I and D translations)
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48 dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
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Embedded supply de-coupling capacitors and Pll filter
components
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High-performance floating point unit - up to 400 MFLOPS
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Single cycle repeat rate for common single precision
operations and some double precision operations
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Two cycle repeat rate for double precision multiply and
double precision combined multiply-add operations
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Single cycle repeat rate for single precision combined
multiply-add operation
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MIPS IV instruction set
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Floating point multiply-add instruction increases
performance in signal processing and graphics
applications
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Conditional moves to reduce branch frequency
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Index address modes (register + register)
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Embedded application enhancements
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Specialized DSP integer Multiply-Accumulate instruction
and 3 operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
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Fully static CMOS design with power down logic
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Standby reduced power mode with WAIT instruction
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5 Watts typical at 3.3V, less than TBD mwatts in Standby
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208-lead CQFP, cavity-up package (F17)
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208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
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179-pin PGA package (
Future Product) (P10)
Store Buffer
Data Set A
Data Tag A
DTLB Physical
Data Tag B
Instruction Set A
Integer Instruction Register
FP Instruction Register
Instruction Set B
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Sys AD
Write Buffer
Read Buffer
Data Set B
DBus
Control
Floating-point
Register File
Joint TLB
Tag
Aux Tag
IntIBus
Floating-point
Coprocessor 0
Unpacker/Packer
MAdd, Add, Sub,Cvt
PC Incrementer
Branch Adder
DVA
Load Aligner
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
Integer Multiply, Divide
In
te
g
e
rC
ont
rol
Instruction TLB Virtual
Fl
o
a
ti
ng
poi
nt
C
o
nt
rol
Phase Lock Loop
Instruction Select
FPIBus
ABus
System/Memory
Control
Program Counter
IVA
Div, SqRt
64-Bit Superscaler Microprocessor
ACT5260