
CD54ACT02, CD74ACT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCHS309B – JANUARY 2001 – REVISED MAY 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Inputs Are TTL-Voltage Compatible
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
±
24-mA Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description
The ’ACT02 devices contain four independent 2-input NOR gates that perform the Boolean function Y = A
or Y = A + B in positive logic.
B
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E
Tube
CD74ACT02E
CD74ACT02E
–55
°
C to 125
°
C
SOIC – M
Tube
CD74ACT02M
ACT02M
Tape and reel
CD74ACT02M96
CDIP – F
Tube
CD54ACT02F3A
CD54ACT02F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
A
OUTPUT
Y
B
H
X
L
X
H
L
L
L
H
logic diagram (positive logic)
2
1A
3
1B
1Y
1
8
3A
9
3B
3Y
10
5
2A
6
2B
2Y
4
11
4A
12
4B
4Y
13
Copyright
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1Y
1A
1B
2Y
2A
2B
GND
V
CC
4Y
4B
4A
3Y
3B
3A
CD54ACT02 . . . F PACKAGE
CD74ACT02 . . . E OR M PACKAGE
(TOP VIEW)