參數資料
| 型號： | AD1380KD |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SNGL 16BIT 32-CDIP |
| 標準包裝： | 1 |
| 位數： | 16 |
| 采樣率（每秒）： | 50k |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 900mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP（0.900"，22.86mm） |
| 供應商設備封裝： | 32-BBDIP-H |
| 包裝： | 管件 |
| 輸入數目和類型： | 16 個單端，雙極；16 個單端，單極 |
Low Cost
16-Bit Sampling ADC
AD1380
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FUNCTIONAL BLOCK DIAGRAM
FEATURES
00764-001
NC = NO CONNECT
32
S/H
OUT
6
+10V
SPAN
7
+20V
SPAN
26
CLOCK
OUT
28
START
CONVERT
4
BIPOLAR
5
COMPARATOR
IN
3
GAIN
ADJ
31
S/H IN
29
+5V
30
DIGITAL
COMMON
2
+15V
8
ANALOG
COMMON
1
–15V
23
10
24
MSB
9
LSB
25
NC
27
BUSY
BIT 2
BIT 15
TIMING CIRCUITRY
ADC
REF
SAMPLE
AND
HOLD
AD1380
Complete sampling 16-bit ADC with reference and clock
50 kHz throughput
±1/2 LSB nonlinearity
Low noise SHA: 300 μV p-p
32-lead hermetic DIP
Parallel output
Low power: 900 μW
APPLICATIONS
Medical and analytical instrumentation
Signal processing
Data acquisition systems
Professional audio
Automatic test equipment (ATE)
Figure 1.
Telecommunications
GENERAL DESCRIPTION
The AD1380 is a complete, low cost 16-bit analog-to-digital
converter, including internal reference, clock and sample/hold
amplifier. Internal thin-film-on-silicon scaling resistors allow
analog input ranges of ±2.5 V, ±5 V, ±10 V, 0 V to +5 V and
0 V to +10 V.
Important performance characteristics of the AD1380 include
maximum linearity error of ±0.003% of FSR (AD1380KD) and
maximum 16-bit conversion time of 14 μs. Transfer
characteristics of the AD1380 (gain, offset and linearity) are
specified for the combined ADC/sample-and-hold amplifier
(SHA), so total performance is guaranteed as a system. The
AD1380 provides data in parallel with corresponding clock and
status outputs. All digital inputs and outputs are TTL or 5 V
CMOS-compatible.
The serial output function is no longer available after date
code 0120.
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