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參數資料
| 型號： | AD484M1644VTA-8I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ascend Semiconductor Corporation(64Mb SDRAM) |
| 中文描述： | 登半導體公司（64MB內存） |
| 文件頁數： | 19/20頁 |
| 文件大小： | 85K |
| 代理商： | AD484M1644VTA-8I |
Preliminary
19
64Mb SDRAM
Ascend Semiconductor Corporation
Operating AC Characteristics--
Continues
( V
DD
= 3.3V +/- 0.3 V, All Operating Range )
Note :
1. All voltages referenced to Vss.
2. For commercial range parts.
3. For industrial range parts.
4. tHZ defines the time at which the output achieve the open circuit
condition and is not referenced to output voltage levels.
5. These parameters account for the number of clock cycle and
depend on the operating frequency of the clock, as follows :
The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number)
6.These parameters are for address/command/data/CLK/CKE.
7. Any “–“ sign on the data means “ No guarantee” .
CL = 1
Parameter
Clock cycle time
Access time from CLK
Data-out hold time
Data-out to high impedance time
CLK high level width
CLK low level width
Input setup time
Input hold time
ACTIVE to ACTIVE command period
ACTIVE to PRECHARGE command period
PRECHARGE to ACTIVE command period
ACTIVE to READ/WRITE delay time
ACTIVE(one) to ACTIVE(another) command
READ/WRITE command to READ/WRITE
command
Data-in to PRECHARGE command
CL = 1
CL = 1
CL = 1
Data-out to high impedance from
PRECHARGE command
Data-in to BURST stop command
Refresh time(4,096 cycle)
CL = 1
Data-out to low impedance time
Symbol
t
CK
t
AC
t
CH
t
CL
t
OH
t
HZ
t
LZ
t
IS
t
IH
t
RC
t
RAS
t
RP
t
RCD
t
RRD
t
CCD
t
DPL
t
BDL
t
ROH
t
REF
-15
Min. Max.
3
3
2
6
1
1
2
90
60
22
100k
25
15
1
15
1
1
1
64
12
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
ms
Notes
5
5
5
5
5
3
4
6
6
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