參數資料
| 型號： | AD7452BRT-R2 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 555KSPS SOT23-8 |
| 標準包裝： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 555k |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 7.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應商設備封裝： | SOT-23-8 |
| 包裝： | 剪切帶 (CT) |
| 輸入數目和類型： | 2 個單端，單極；1 個差分，單極 |
| 其它名稱： | AD7452BRT-R2CT |
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Differential Input, 555 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7452
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
Specified for VDD of 3 V and 5 V
Low power at max throughput rate:
3.3 mW max at 555 kSPS with 3 V supplies
7.25 mW max at 555 kSPS with 5 V supplies
Fully differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI/QSPI/MICROWIRE/DSP compatible
Power-down mode: 1 A max
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control
GENERAL DESCRIPTION
The AD74521 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
fully differential analog input. This part operates from a single
3 V or 5 V power supply and features throughput rates up to
555 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the VREF pin and can be varied from 100 mV to
3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the
user can select a variety of input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled on
the falling edge of CS, and the conversion is also initiated at this
point.
FUNCTIONAL BLOCK DIAGRAM
VREF
T/H
CONTROL LOGIC
12-BIT
SUCCESSIVE
ADC
GND
SCLK
SDATA
CS
VDD
AD7452
VIN+
VIN–
APPROXIMATION
03154-A
-001
Figure 1.
The SAR architecture of this part ensures that there are no
pipeline delays.
The AD7452 uses advanced design techniques to achieve very
low power dissipation.
PRODUCT HIGHLIGHTS
1.
Operation with Either 3 V or 5 V Power Supplies.
2.
High Throughput with Low Power Consumption. With a
3 V supply, the AD7452 offers 3.3 mW max power
consumption for 555 kSPS throughput.
3.
Fully Differential Analog Input.
4.
Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.
5.
Variable Voltage Reference Input.
6.
No Pipeline Delay.
7.
Accurate Control of the Sampling Instant via a CS Input
and Once-Off Conversion Control.
8.
ENOB > 8 Bits Typically with 100 mV Reference.
1 Protected by U.S. Patent Number 6,681,332.
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