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參數(shù)資料
| 型號： | AD7621 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC |
| 中文描述： | 16位，1 LSB INL和3 MSPS的PulSAR系列ADC的 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大小： | 265K |
| 代理商： | AD7621 |
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REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
–8–
of the host interface (2.5 V or 3 V).
Digital Power. Nominally at 2.5 V.
Digital Power Ground.
When SER/
PAR
is LOW, this output is used as Bit 8 of the Parallel PortData
Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a serial
data output synchronized to SCLK. Conversion results are stored in an on-chip
register. The AD7621 provides the conversion result, MSB first, from its internal
shift register. The data format is determined by the logic level of OB/
2C
.
In serial mode, when EXT/
INT
is LOW, SDOUT is valid on both edges of SCLK.
In serial mode, when EXT/
INT
is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the
next falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the
next rising edge.
When SER/
PAR
is LOW, this output is used as the Bit 9 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this pin, part of the serial port, is used as a serial data
clock input or output, dependent upon the logic state of the EXT/
INT
pin. The
active edge where the data SDOUT is updated depends upon the logic state of the
INVSCLK pin.
When SER/
PAR
is LOW, this output is used as the Bit 10 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a digital
output frame synchronization for use with the internal data clock (EXT/
INT
= Logic
LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven
HIGH and remains HIGH while SDOUT output is valid. When a read sequence is
initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while
SDOUT output is valid.
When SER/
PAR
is LOW, this output is used as the Bit 11 of the ParallelPort Data
Output Bus.
When SER/
PAR
is HIGH and when EXT/
INT
is HIGH, this output, part of the
serial port, is used as a incomplete read error flag. In slave mode, when a data
read is started and not complete when the following conversion is complete, the
current data is lost and RDERROR is pulsed high.
Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs
regard less of the interface mode.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH
until the conversion is complete and the data is latched into the on-chip shift register.
The falling edge of BUSY could be used as a data ready clock signal.
Must be tied to digital ground.
Read Data. When
CS
and
RD
are both LOW, the interface parallel or serial output
bus is enabled.
Chip Select. When
CS
and
RD
are both LOW, the interface parallel or serial output
bus is enabled.
CS
is also used to gate the external clock.
Reset Input. When set to a logic HIGH, reset the AD7621. Current conversion if any
is aborted. If not used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and
conversions are inhibited after the current one is completed.
Start Conversion. A falling edge on
CNVST
puts the internal sample/hold into the
hold state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP
LOW), if
CNVST
is held LOW when the acquisition phase
(
t
8
) is complete, the
internal sample/hold is put into the hold state and a conversion is immediately
started.
Must be tied to analog ground.
Reference Input Voltage and Internal Reference Buffer Output. Apply an external
reference on this pin if the internal reference buffer is not used. Should be decoupled
effectively with or without the internal buffer.
Reference Input Analog Ground.
19
20
21
DVDD
DGND
D8
P
P
DO
or SDOUT
22
D9
DI/O
or SCLK
23
D10
DO
or SYNC
24
D11
DO
or RDERROR
25–28
D[12:15]
DO
29
BUSY
DO
30
31
DGND
RD
P
DI
32
CS
DI
33
RESET
DI
34
PD
DI
35
CNVST
DI
36
37
AGND
REF
P
AI
38
REFGND
AI
Pin No.
Mnemonic
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7621ACP | 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC |
| AD7621ACPRL | 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC |
| AD7621AST | 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC |
| AD7621ASTRL | 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC |
| AD7628 | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7621ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 3Msps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:16-BIT, 1 LSB INL, 3 MSPS PULSAR- ADC - Bulk |
| AD7621ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 3Msps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R |
| AD7621ACPZ | 功能描述:IC ADC 16BIT 2MSPS DIFF 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 其它有關(guān)文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7621ACPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 2 LSB INL, 3 MSPS PulSAR?? ADC |
| AD7621ACPZRL | 功能描述:IC ADC 16BIT 2MSPS DIFF 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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