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參數資料
型號: AD7621ACPRL
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC
中文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48
封裝: MO-220-VKKD-2, LFCSP-48
文件頁數: 21/26頁
文件大小: 265K
代理商: AD7621ACPRL
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
–21–
PARALLEL INTERFACE
The AD7621 is configured to use the parallel interface
with either a 16-bit or 8-bit bus width. The data can be
read either after each conversion, which is during the
next acquisition phase, or during the following conversion
as shown, respectively, in Figure 15 and Figure 16. When
the data is read during the conversion, however, it is rec-
ommended that it is read only during the first half of the
conversion phase. That avoids any potential feedthrough
between voltage transients on the digital interface and the
most critical analog conversion circuitry.
CURRENT
CONVERSION
BUSY
DATA
BUS
CS
RD
t
12
t
13
Figure 15. Slave Parallel Data Timing for Reading
(Read After Convert)
t
1
t
3
t
4
CS = 0
CNVST, RD
BUSY
PREVIOUS
CONVERSION
t
12
t
13
DATA
BUS
Figure 16. Slave Parallel Data Timing for Reading
(Read During Convert)
CS
A0, A1
Pins D[15:8]
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
t12
t12
t13
Pins D[7:0]
RD
Figure 17. 8-Bit and 16-Bit Parallel Interface
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
1
2
3
16
D15
D14
D2
D1
D0
X
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
25
t
30
15
14
Figure 18. Master Serial Data Timing for Reading (Read After Convert)
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