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參數(shù)資料
| 型號(hào)： | AD7641ACPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC48 |
| 封裝： | MO-220-VKKD, LFCSP-48 |
| 文件頁(yè)數(shù)： | 19/24頁(yè) |
| 文件大小： | 324K |
| 代理商： | AD7641ACPRL |
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Preliminary Technical Data
AD7641
Rev. Pr E | Page 19 of 24
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t
3
t
1
t
17
t
14
t
19
t
20
t
21
t
24
t
26
t
25
t
27
t
23
t
22
t
16
t
15
D17
D16
D2
D1
D0
X
1
2
3
16
17
18
t
18
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
Figure 20. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
External Discontinuous Clock Data Read After
Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes. Figure 21 shows the detailed timing diagrams of this
method. After a conversion is complete, indicated by BUSY
returning low, the result of this conversion can be read while
both CS and RD are low. The data is shifted out, MSB first, with
18 clock pulses and is valid on both rising and falling edge of
the clock.
Among the advantages of this method, the conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 80 MHz which accommodates both slow digital host
interface and the fastest serial reading.
Finally, in this mode only, the AD7641 provides a “daisy-chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing
component count and wiring connections when desired as, for
instance, in isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 23. Simultaneous sampling is possible by using a
common CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT.Hence, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter on
the next SCLK cycle.
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