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參數資料
| 型號： | AD7655 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | Low Cost 4-Channel 1 MSPS 16-Bit ADC |
| 中文描述： | 低成本4通道1 MSPS的16位ADC |
| 文件頁數： | 16/20頁 |
| 文件大?。?/td> | 684K |
| 代理商： | AD7655 |
REV. 0
–16–
AD7655
MASTER SERIAL INTERFACE
Internal Clock
The AD7655 is configured to generate and provide the serial
data clock SCLK when the EXT/
INT
pin is held low. The AD7655
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired.
The output data is valid on both the rising and falling edge of
the data clock. Depending on RDC/SDIN input, the data can be
read after each conversion or during the following conversion.
Figures 15 and 16 show the detailed timing diagrams of these
two modes.
Usually, because the AD7655 is used with a fast throughput, the
mode master, read during conversion is the most recommended
serial mode when it can be used.
In read after conversion mode, it should be noted that unlike in
other modes, the signal BUSY returns low after the 32 data bits
are pulsed out and not at the end of the conversion phase, which
results in a longer BUSY width. One advantage of this mode is
t
3
BUSY
CS
,
RD
CNVST
SYNC
SCLK
SDOUT
1
2
16
30
31
32
CH A
D15
CH A
D14
t
30
CH B
D2
CH B
D1
CH B D0
X
EXT/
INT
= 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
21
t
27
t
22
t
23
t
29
t
36
t
25
t
26
t
28
t
37
t
32
t
31
t
33
t
34
A/
B
= 1
EOC
t
12
t
13
17
t
35
Figure 15. Master Serial Data Timing for Reading (Read after Convert)
EXT/
INT
= 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t
3
t
1
t
24
t
21
t
26
t
27
t
28
t
31
t
33
t
32
t
34
t
30
t
29
t
23
t
22
CH A
D15
X
1
2
16
1
2
t
25
BUSY
SYNC
SCLK
SDOUT
CS
,
RD
CNVST
16
CH B
D15
CH A D0
CH A
D14
CH B
D14
CH B D0
A/
B
= 1
EOC
t
10
t
11
t
13
t
12
Figure 16. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
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