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參數資料
| 型號： | AD7660AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS CMOS ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數： | 16/20頁 |
| 文件大小： | 218K |
| 代理商： | AD7660AST |
REV. 0
AD7660
–16–
which results in a longer BUSY width. In read-during-conversion
mode, the serial clock and data toggle at appropriate instants,
which minimizes potential feedthrough between digital activity
and the critical conversion decisions.
SLAVE SERIAL INTERFACE
External Clock
The AD7660 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
INT
pin is
held high. In this mode, several methods can be used to read the
data. When
CS
and
RD
are both low, the data can be read after
each conversion or during the following conversion. The exter-
nal clock can be either a continuous or discontinuous clock. A
discontinuous clock can be either normally high or normally low
when inactive. Figure 18 and Figure 20 show the detailed timing
diagrams of these methods. Usually, because the AD7660 has a
longer acquisition phase than the conversion phase, the data are
read immediately after conversion.
While the AD7660 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is particu-
larly important during the second half of the conversion phase
because the AD7660 provides error correction circuitry that can
correct for an improper bit decision made during the first half of
the conversion phase. For this reason, it is recommended that when
an external clock is being provided, it is a discontinuous clock
that is toggling only when BUSY is low or, more importantly,
that it does not transition during the latter half of BUSY high.
t
3
BUSY
CS
,
RD
CNVST
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
1
2
3
14
15
16
D15
D14
D2
D1
D0
X
EXT/
INT
= 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
25
t
30
Figure 16. Master Serial Data Timing for Reading (Read after Convert)
EXT/
INT
= 0
CS
,
RD
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
CNVST
BUSY
SYNC
SCLK
SDOUT
t
3
t
1
t
17
t
14
t
19
t
20
t
21
t
24
t
26
t
25
t
27
t
23
t
22
t
16
t
15
D15
D14
D2
D1
D0
X
1
2
3
14
15
16
t
18
Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
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| AD7660ASTZ | 功能描述:IC ADC 16BIT UNIPOLAR 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7660ASTZ | 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
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