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參數資料
| 型號： | AD7660ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS CMOS ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數： | 14/20頁 |
| 文件大小： | 218K |
| 代理商： | AD7660ASTRL |
REV. 0
AD7660
–14–
THROUGHPUT
–
SPS
100
10
P
–
1
100
0.01
10
1000
10000
100000
0.1
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7660 is controlled by the signal
CNVST
which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The
CNVST
signal operates independently of
CS
and
RD
signals.
For a true sampling application, the recommended operation of
the
CNVST
signal is the following:
CNVST
must be held high from the previous falling edge of
BUSY, and during a minimum delay corresponding to the
acquisition time t8; then, when
CNVST
is brought low, a con-
version is initiated and BUSY signal goes high until the completion
of the conversion. Although
CNVST
is a digital signal, it should
be designed with special care with fast, clean edges and levels,
with minimum overshoot and undershoot or ringing. For appli-
cations where the SNR is critical, the
CNVST
signal should
have a very low jitter. Some solutions to achieve this are to use a
dedicated oscillator for
CNVST
generation or, at least, to clock
it with a high frequency low jitter clock as shown in Figure 6.
For other applications, conversions can be automatically initi-
ated. If
CNVST
is held low when BUSY is low, the AD7660
controls the acquisition phase and then automatically initiates a
new conversion. By keeping
CNVST
low, the AD7660 keeps
the conversion process running by itself. It should be noted that
the analog input has to be settled when BUSY goes low. Also, at
power-up,
CNVST
should be brought low once to initiate the
conversion process. In this mode, the AD7660 could sometimes
run slightly faster than the guaranteed limit of 100 kSPS.
DIGITAL INTERFACE
The AD7660 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7660 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7660
to the host system interface digital supply. Finally, by using the
OB/
2C
input pin, both two’s complement or straight binary
coding can be used.
The two signals
CS
and
RD
control the interface.
CS
and
RD
have a similar effect because they are OR’d together internally.
When at least one of these signals is high, the interface outputs
are in high impedance. Usually,
CS
allows the selection of each
AD7660 in multicircuits applications and is held low in a single
AD7660 design.
RD
is generally used to enable the conversion
result on the data bus.
t
2
t
1
t
3
t
5
t
4
t
6
t
7
t
8
CNVST
BUSY
MODE
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 11. Basic Conversion Timing
t
9
t
8
RESET
DATA
BUSY
CNVST
Figure 12. RESET Timing
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相關代理商/技術參數 |
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| AD7660ASTRLZ | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel/Serial 48-Pin LQFP T/R |
| AD7660ASTZ | 功能描述:IC ADC 16BIT UNIPOLAR 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7660ASTZ | 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
| AD7660ASTZRL | 功能描述:IC ADC 16BIT UNIPOLAR 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7661 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC |
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