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參數資料
| 型號： | AD7682 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 8-Channel, 250 kSPS PulSAR㈢ ADC. |
| 中文描述： | 16位，8通道，250 kSPS的PulSAR系列㈢ADC的。 |
| 文件頁數： | 8/20頁 |
| 文件大小： | 2041K |
| 代理商： | AD7682 |
AD7689
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. PrC | Page 8 of 20
PIN 1
INDICATOR
1
2
3
4
5
VDD
REF
REFIN
GND
GND
13 SCK
12 DIN
11 CNV
14 SDO
15 VIO
6
I
7
I
8
I
1
C
9
I
1
1
2
1
1
TOP VIEW
0
Figure 4. 20-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
1, 20
VDD
Type
1
P
Description
Power Supply. Nominally 2.5 V to 5.5 V when using an external reference, and decoupled with
10 μF and 100 nF capacitors.
When using the internal reference for 2.5V output, the minimum should be 2.7V.
When using the internal reference for 4.096V output, the minimum should be 4.5V.
Reference Input/Output. See the Voltage Reference Output/Input section.
When the internal reference is enabled, this pin produces a selectable system reference = 2.5V or
4.096V.
When the internal reference is disabled and the buffer is enabled, REF produces a buffered
version of the voltage present on the REFIN pin (4.096V max.) useful when using low cost, low
power references.
For improved drift performance, connect a precision reference to REF (0.5V to VDD).
For any reference method, this pin needs decoupling with an external a 22 μF capacitor
connected as close to REF as possible. See the Reference Decoupling section.
Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input
section.
When using the internal reference, the internal unbuffered reference voltage is present and
needs decoupling with a 0.1μF capacitor.
When using the internal reference buffer, apply a source between 0.5V to 4.096V which is
buffered to the REF pin as described above.
Power Supply Ground.
Channel 4 through Channel 7 Analog Inputs.
Common Channel Input. All channels [7:0] can be referenced to a common mode point of 0 V or
V
REF
/2 V.
Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is
held high, the BUSY indictor is enabled.
Data Input. This input is used for writing to the 14-bit configuration register. The configuration
register can be written to during and after conversion.
Serial Data Clock Input. This input is used to clock out the data on ADO and clock in data on DIN
in an MSB first fashion.
Serial Data Output. The conversion result is output on this pin synchronized to SCK. In unipolar
modes, conversion results are straight binary; in bipolar modes conversion results are twos
complement.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
Channel 0 through Channel 3 Analog Inputs.
2
REF
AI/O
3
REFIN
AI/O
4, 5
6 - 9
10
GND
IN4 – IN7
COM
AI
AI
AI
11
CNV
DI
12
DIN
DI
13
SCK
DI
14
SDO
DO
15
VIO
P
16 - 19
1
AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
IN0 – IN3
AI
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