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參數(shù)資料
| 型號(hào)： | AD7701ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | LC2MOS 16-Bit A/D Converter |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MO-150AH, SSOP-28 |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大小： | 312K |
| 代理商： | AD7701ARS |
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AD7701
REV. D
–10–
INPUT SIGNAL CONDIT IONING
Reference voltages from +1 V to +3 V may be used with the
AD7701, with little degradation in performance. Input ranges
that cannot be accommodated by this range of reference voltages
may be achieved by input signal conditioning. T his may take the
form of gain to accommodate a smaller signal range, or passive
attenuation to reduce a larger input voltage range.
Source Resistance
If passive attenuators are used in front of the AD7701, care
must be taken to ensure that the source impedance is suffi-
ciently low. T he AD7701 has an analog input with over 1 G
dc input resistance. In parallel with this there as a small dy-
namic load which varies with the clock frequency (see Figure
13). Each time the analog input is sampled, a 10 pF capacitor
draws a charge packet of maximum 1 pC (10 pF
×
100 mV)
A
IN
R1
R2
C
EXT
AGND
AD7701
V
OS
≤
100mV
C
IN
10pF
Figure 13. Equivalent Input Circuit and Input Attenuator
from the analog source with a frequency f
CLK IN
/256. For a
4.096 MHz CLK IN, this yields an average current draw of
16 nA. After each sample the AD7701 allows 62 clock periods
for the input voltage to settle. T he equation which defines
settling time is:
V
O
= V
IN
[1 – e
–t/RC
]
where:
V
O
is the final settled value,
V
IN
is the value of the input signal,
R
is
the value of the input source resistance,
C
is the 10 pF sample capacitor,
t
is equal to 62/f
CLK IN
.
From this, the following equation can be developed which gives
the maximum allowable source resistance, R
S(MAX )
, for an error
of
V
E
:
R
S
(
MAX
)
=
62
f
CLKIN
×
(10
pF
)
×
ln
(100
mV
/
V
E
)
Provided the source resistance is less than this value, the analog
input will settle within the desired error band in the requisite 62
clock periods. Insufficient settling leads to offset errors. T hese
can be calibrated in system calibration schemes.
If a limit of 10
μ
V (0.25 LSB at 16 bits) is set for the maximum
offset voltage, then the maximum allowable source resistance is
160 k
from the above equation, assuming that there is no
external stray capacitance.
An RC filter may be added in front of the AD7701 to reduce
high frequency noise. With an external capacitor added from
A
IN
to AGND, the following equation will specify the maximum
allowable source resistance:
T he practical limit to the maximum value of source resistance is
thermal (Johnson) noise. A practical resistor may be modeled as
an ideal (noiseless) resistor in series with a noise voltage source
or in parallel with a noise current source.
V
n
=
√
4 kTRf
Volts
i
n
=
√
4 kTf / R
Amperes
where:
k
is Boltzmann’s constant (1.38
×
10
–23
J/K )
and
T
is temperature in degrees K elvin (
°
C + 273).
Active signal conditioning circuits such as op amps generally do
not suffer from problems of high source impedance. T heir open
loop output resistance is normally only tens of ohms and, in any
case, most modern general purpose op amps have sufficiently
fast closed loop settling time for this not to be a problem. Offset
voltage in op amps can be eliminated in a system calibration
routine. With the wide dynamic range and small LSB size of the
AD7701, noise can also be a problem, but the digital filter will
reject most broadband noise above its cutoff frequency. How-
ever, in certain applications there may be a need for analog
input filtering.
R
S
(
Max
)
=
62
f
CLKIN
×
(
C
IN
+
C
EX T
)
×
ln
100
mV
×
C
IN
/(
C
IN
+
C
EX T
)
V
E
Antialias Considerations
T he digital filter of the AD7701 does not provide any rejection
at integer multiples of the sampling frequency (nf
CLK lN
/256,
where n = 1, 2, 3 . . . ).
With a 4.096 MHz master clock there are narrow (
±
10 Hz)
bands at 16 kHz, 32 kHz, 48 kHz, etc., where noise passes
unattenuated to the output.
However, due to the AD7701’s high oversampling ratio of 800
(16 kHz to 20 Hz) these bands occupy only a small fraction of
the spectrum, and most broadband noise is filtered. T he
reduction in broadband noise is given by:
e
OUT
=
e
IN
2
f
C
/
f
S
=
0.035
e
IN
where:
e
lN
and
e
OUT
are rms noise terms referred to the input
f
C
is the filter –3 dB corner frequency
(f
CLK IN
/409600)
and
f
S
is
the sampling frequency (f
CLK IN
/256).
Since the ratio of f
S
to f
CLK IN
is fixed, the digital filter reduces
broadband white noise by 96.5% independent of the master
clock frequency.
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