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參數資料
| 型號： | AD7703BQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 20-Bit A/D Converter |
| 中文描述： | 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數： | 15/16頁 |
| 文件大小： | 251K |
| 代理商： | AD7703BQ |
AD7703
REV. D
–15–
SY NCHRONOUS E X T E RNAL CLOCK MODE (SE C)
T he SEC mode (MODE pin grounded) is designed for direct
interface to the synchronous serial ports of industry standard
microprocessors such as the 68HC11 and 68HC05. T he SEC
mode also allows customized interfaces, using I/O port pins, to
microprocessors that do not have a direct fit with the AD7703’s
other mode.
As shown in Figure 17, a falling edge on
CS
enables the serial
data output with the MSB initially valid. Subsequent data bits
change on the falling edge of an externally supplied SCLK .
After the LSB has been transmitted,
DRDY
and SDAT A go
three-state. If
CS
is low and the AD7703 is still transmitting
data when a new data word becomes available, the old data
word continues to be transmitted and the new data is lost.
If
CS
is taken high at any time during data transmission,
SDAT A will go three-state immediately. If
CS
returns low, the
AD7703 will continue transmission with the same data bit. If
transmission has not been initiated and completed by the time
the next data word becomes available, and if
CS
is high,
DRDY
will return high for four clock cycles, then fall as the new word is
loaded into the output register.
DIGIT AL NOISE AND OUT PUT LOADING
As mentioned earlier, the AD7703 divides its internal timing
into two distinct phases, analog sampling and settling and digital
computation. In the SSC mode, data is transmitted only during
the digital computation periods, to minimize the effects of
digital noise on analog performance. In the SEC mode data
transmission is externally controlled, so this automatic safeguard
does not exist. T o compensate, the AD7703 should be
synchronized to the digital system clock via CLK IN when used
in the SEC mode.
Whatever mode of operation is used, resistive and capacitive
loads on digital outputs should be minimized in order to reduce
crosstalk between analog and digital portions of the circuit. For
this reason connection to low-power CMOS logic such as one of
the 4000 series or 74C families is recommended.
DRDY (O)
SDATA (O)
DB19 (MSB)
DB18
DB2
DB1
DB0 (LSB)
HI-Z
SCLK (O)
HI-Z
CS (I)
DB17
Figure 17. Timing Diagram for the SEC Mode
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