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參數(shù)資料
型號(hào)： AD7706BN
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
中文描述： 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP16
封裝： 0.300 INCH, PLASTIC, MS-001AB, DIP-16
文件頁數(shù)： 2/32頁
文件大小： 264K
代理商： AD7706BN
–2–
REV. A
AD7705/AD7706–SPECIFICATIONS
(V
DD
= +3 V or 5 V, REF IN(+) = +1.225V with V
DD
= 3 V and +2.5 V
with V
DD
= 5 V; REFIN(–) = GND; MCLK IN = 2.4576MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
B Version
1
Units
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
Output Noise
Integral Nonlinearity
2
Unipolar Offset Error
Unipolar Offset Drift
4
Bipolar Zero Error
Bipolar Zero Drift
4
16
See Tables I and III
±
0.003
See Note 3
0.5
See Note 3
0.5
0.1
See Note 3
0.5
See Note 3
0.5
±
0.003
1
0.6
Bits min
Guaranteed by Design. Filter Notch < 60Hz
Depends on Filter Cutoffs and Selected Gain
Filter Notch < 60Hz. Typically
±
0.0003%
% of FSR max
μ
V/
°
C typ
μ
V/
°
C typ
μ
V/
°
C typ
For Gains 1, 2 and 4
For Gains 8, 16, 32, 64 and 128
Positive Full-Scale Error
5
Full-Scale Drift
Gain Error
7
Gain Drift
4, 8
Bipolar Negative Full-Scale Error
2
Bipolar Negative Full-Scale Drift
4
μ
V/
°
C typ
ppm of FSR/
°
C typ
% of FSR typ
μ
V/
°
C typ
μ
V/
°
C typ
Typically
±
0.001%
For Gains of 1 to 4
For Gains of 8 to 128
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)
V
DD
= 5 V
Gain = 2
Gain = 4
Gain = 8
v
128
V
DD
= 3 V
Gain = 2
Gain = 4
Gain = 8
v
128
Normal-Mode 50 Hz Rejection
2
Normal-Mode 60 Hz Rejection
2
Common-Mode 50 Hz Rejection
2
Common-Mode 60 Hz Rejection
2
Absolute/Common-Mode REF IN Voltage
2
Absolute/Common-Mode AIN Voltage
2, 9
Specifications for AIN and REF IN Unless Noted
96
105
110
130
dB typ
dB typ
dB typ
dB typ
105
110
120
130
98
98
150
150
GND to V
GND – 30 mV
V
+ 30mV
GND + 50mV
V
DD
– 1.5V
1
10
0 to +V
/GAIN
11
±
V
/GAIN
GAIN
×
f
CLKIN
/64
f
CLKIN
/8
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
V min to V max
V min
V max
V min
V max
nA max
pF max
nom
nom
For Filter Notches of 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 20 Hz, 60 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 20 Hz, 60 Hz,
±
0.02
×
f
NOTCH
BUF Bit of Setup Register = 0
Absolute/Common-Mode AIN Voltage
2, 9
BUF Bit of Setup Register = 1
AIN DC Input Current
2
AIN Sampling Capacitance
2
AIN Differential Voltage Range
10
Unipolar Input Range (B/U Bit of Setup Register = 1)
Bipolar Input Range (B/U Bit of Setup Register = 0)
For Gains of 1 to 4
For Gains of 8 to 128
AIN Input Sampling Rate, f
S
Reference Input Range
REF IN(+) – REF IN(–) Voltage
1/1.75
V min/max
V
= 2.7 V to 3.3 V. V
REF
= 1.225
±
1% for Specified
Performance
V
= 4.75 V to 5.25 V. V
REF
= 2.5
±
1% for Specified
Performance
REF IN(+) – REF IN(–) Voltage
1/3.5
V min/max
REF IN Input Sampling Rate, f
S
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
MCLK
All Inputs Except SCLK and MCLK IN
V
INL
, Input Low Voltage
f
CLKIN
/64
±
1
±
10
μ
A max
μ
A max
Typically
±
20 nA
Typically
±
2
μ
A
0.8
0.4
2.0
V max
V max
V min
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V and 5 V
V
DD
= 5 V NOMINAL
V
, Input High Voltage
SCLK Only (Schmitt Triggered Input)
V
T+
V
T–
V
– V
SCLK Only (Schmitt Triggered Input)
V
T+
V
T–
V
– V
MCLK IN Only
V
INL
, Input Low Voltage
V
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
1.4/3
0.8/1.4
0.4/0.8
V min/V max
V min/V max
V min/V max
V
DD
= 3 V NOMINAL
1/2.5
0.4/1.1
0.375/0.8
V min/V max
V min/V max
V min/V max
V
DD
= 5 V NOMINAL
0.8
3.5
V max
V min
V
DD
= 3 V NOMINAL
0.4
2.5
V max
V min
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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