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參數(shù)資料
| 型號： | AD7707 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| 中文描述： | 3 V / 5號第五，1毫瓦3 -10 V輸入范圍通道16位Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 24/40頁 |
| 文件大小： | 316K |
| 代理商： | AD7707 |
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REV. A
AD7707
–24–
on the AIN voltage before
DRDY
goes low. If
DRDY
is low
before (or goes low during) the calibration command write to
the Setup Register, it may take up to one modulator cycle
(MCLKIN/128) before
DRDY
goes high to indicate that cali-
bration is in progress. Therefore,
DRDY
should be ignored for
up to one modulator cycle after the last bit is written to the
Setup Register in the calibration command.
In the unipolar mode, the system calibration is performed be-
tween the two endpoints of the transfer function; in the bipolar
mode, it is performed between midscale (zero differential volt-
age) and positive full-scale.
The fact that the system calibration is a two-step calibration
offers another feature. After the sequence of a full system cali-
bration has been completed, additional offset or gain calibra-
tions can be performed by themselves to adjust the system zero
reference point or the system gain. Calibrating one of the pa-
rameters, either system offset or system gain, will not affect the
other parameter.
System calibration can also be used to remove any errors from
source impedances on the analog input when the part is used in
unbuffered mode. A simple R, C antialiasing filter on the front
end may introduce a gain error on the analog input voltage, but
the system calibration can be used to remove this error.
Span and Offset Limits on the Low Level Input Channels
AIN1 and AIN2
Whenever a system calibration mode is used, there are limits on
the amount of offset and span which can be accommodated.
The overriding requirement in determining the amount of offset
and gain that can be accommodated by the part is the require-
ment that the positive full-scale calibration limit is < 1.05
×
V
REF
/GAIN. This allows the input range to go 5% above the
nominal range. The built-in headroom in the AD7707’s analog
modulator ensures that the part will still operate correctly with a
positive full-scale voltage that is 5% beyond the nominal.
The input span in both the unipolar and bipolar modes has a
minimum value of 0.8
×
V
REF
/GAIN and a maximum value of
2.1
×
V
REF
/GAIN. However, the span (which is the difference
between the bottom of the AD7707’s input range and the top of
its input range) has to take into account the limitation on the
positive full-scale voltage. The amount of offset which can be
accommodated depends on whether the unipolar or bipolar
mode is being used. Once again, the offset has to take into ac-
count the limitation on the positive full-scale voltage. In unipo-
lar mode, there is considerable flexibility in handling negative
offsets. In both unipolar and bipolar modes, the range of posi-
tive offsets that can be handled by the part depends on the
selected span. Therefore, in determining the limits for system
zero-scale and full-scale calibrations, the user has to ensure that
the offset range plus the span range does exceed 1.05
×
V
REF
/
GAIN. This is best illustrated by looking at a few examples.
If the part is used in unipolar mode with a required span of
0.8
×
V
REF
/GAIN, the offset range the system calibration can
handle is from –1.05
×
V
REF
/GAIN to +0.25
×
V
REF
/GAIN. If
the part is used in unipolar mode with a required span of V
REF
/
GAIN, the offset range the system calibration can handle is
from –1.05
×
V
REF
/GAIN to +0.05
×
V
REF
/GAIN. Similarly, if
the part is used in unipolar mode and required to remove an
offset of 0.2
×
V
REF
/GAIN, the span range the system calibra-
tion can handle is 0.85
×
V
REF
/GAIN.
AD7707 LOW LEVEL
INPUT CHANNEL
INPUT RANGE
(0.8
3
V
REF
/GAIN TO
2.1
3
V
REF
/GAIN)
UPPER LIMIT ON
AD7707 INPUT VOLTAGE
NOMINAL ZERO
SCALE POINT
OFFSET CALIBRATIONS MOVE
INPUT RANGE UP OR DOWN
LOWER LIMIT ON
AD7707 INPUT VOLTAGE
–1.05
3
V
REF
/GAIN
–0V DIFFERENTIAL
GAIN CALIBRATIONS EXPAND
OR CONTRACT THE
AD7707 INPUT RANGE
1.05
3
V
REF
/GAIN
Figure 15. Span and Offset Limits for Low Level Input
Channels AIN1 and AIN2
If the part is used in bipolar mode with a required span of
±
0.4
×
V
REF
/GAIN, the offset range the system calibration can handle
is from –0.65
×
V
REF
/GAIN to +0.65
×
V
REF
/GAIN. If the part is
used in bipolar mode with a required span of
±
V
REF
/GAIN,
then the offset range which the system calibration can handle is
from –0.05
×
V
REF
/GAIN to +0.05
×
V
REF
/GAIN. Similarly, if
the part is used in bipolar mode and required to remove an
offset of
±
0.2
×
V
REF
/GAIN, the span range the system calibra-
tion can handle is
±
0.85
×
V
REF
/GAIN. Figure 15 shows a
graphical representation of the span and offset limits for the low
level input channels.
Span and Offset Limits on the High Level Input Channel
AIN3
The exact same reasoning as above can be applied to the high
level input channel. When using the high level channel the at-
tenuator provides an attenuation factor of 8. All span and offset
limits should be multiplied by a factor of 8. Therefore, the range
of input span in both the unipolar and bipolar modes has a
minimum value of 6.4
×
V
REF
/GAIN and a maximum value of
16.8
×
V
REF
/GAIN. The offset range plus the span range cannot
exceed 8.4
×
V
REF
/GAIN.
Power-Up and Calibration
On power-up, the AD7707 performs an internal reset that sets
the contents of the internal registers to a known state. There are
default values loaded to all registers after power-on or reset.
The default values contain nominal calibration coefficients for
the calibration registers. However, to ensure correct calibration
for the device, a calibration routine should be performed after
power-up. A calibration should be performed if the update-rate
or gain are changed.
The power dissipation and temperature drift of the AD7707 are
low and no warm-up time is required before the initial calibra-
tion is performed. However, if an external reference is being
used, this reference must have stabilized before calibration is
initiated. Similarly, if the clock source for the part is generated
from a crystal or resonator across the MCLK pins, the start-up
time for the oscillator circuit should elapse before a calibration
is initiated on the part (see the following).
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| AD7707BR | 功能描述:IC ADC 16BIT 3CH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7707BR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 20-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.5KSPS 16BIT SERL 20SOIC W - Tape and Reel |
| AD7707BR-REEL7 | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 20-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.5KSPS 16BIT SERL 20SOIC W - Tape and Reel |
| AD7707BRU | 功能描述:IC ADC 16BIT 3CH 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7707BRU-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 20-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.5KSPS 16BIT SERL 20TSSOP - Tape and Reel |
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