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參數資料
| 型號： | AD7709BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LGE Kit Series; Functions: Continuous light; Rated Voltage: 120V AC; Style: Power Unit; Diameter: 100; Applicable Model: LGE |
| 中文描述： | 4-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | PLASTIC, MO-153AD, TSSOP-24 |
| 文件頁數： | 6/17頁 |
| 文件大小： | 248K |
| 代理商： | AD7709BRU |
AD7709
TIMNGCHARACTERISTICS
1, 2
(V
DD
= +3V ±10% or V
DD
= +5V ±10%;GND = 0 V:X
TAL
= 32.768kHz; Input Logic 0 = 0 V, Logic 1 = V
DD
–6–
REV. PrA J anuary 2001
PRELIMINARY TECHNICAL DATA
unless otherwse noted)
Limit at T
MIN
, T
MAX
(B Version)
Parameter
Units
Conditions/Comments
t
1
t
2
Read Operation
t
3
t
4
32.768
50
kHz typ
ns min
C rystal Oscillator Frequency.
RESET
Pulse Width
0
0
ns min
ns min
RDY
to
CS
Setup T ime
CS
Falling Edge to SCLK Active Edge Setup
T ime
3
SCLK Active Edge to Data Valid Delay
3
V
DD
= +4.5 V to +5.5 V
V
DD
= +2.7 V to +3.6 V
CS
Falling Edge to Data Valid Delay
3
V
DD
= +4.5 V to +5.5 V
V
DD
= +2.7 V to +3.6 V
SCL K High Pulse Width
SCLK Low Pulse Width
CS
Rising Edge to SCLK Inactive Edge Hold
T ime
3
Bus Relinquish T ime after SCLK Inactive Edge
3
t
54
0
60
80
0
60
80
100
100
0
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns min
ns min
t
5A4, 5
t
6
t
7
t
8
t
96
10
80
100
ns min
ns max
ns max
t
10
Write Operation
t
11
SCLK Active Edge to
RDY
High
3, 7
0
ns min
CS
Falling Edge to SCLK Active Edge Setup
T ime
3
Data Valid to SCLK Edge Setup T ime
Data Valid to SCLK Edge Hold T ime
SCL K High Pulse Width
SCLK Low Pulse Width
CS
Rising Edge to SCLK Edge Hold T ime
t
12
t
13
t
14
t
15
t
16
30
25
100
100
0
ns min
ns min
ns min
ns min
ns min
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figures 1 and 2.
3
SCLK active edge is falling edge of SCLK.
4
These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the V
or V
OH
limits.
5
This specification only comes into play if
CS
goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove effects of charging or
discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
7
RDY
returns high after the first read from the device after an output update. The same data can be read again, if required, while
RDY
is high, although care should be taken that subsequent reads do not occur close to
the next output update.
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