- 您現在的位置：買賣IC網 > PDF目錄373914 > AD7712AN (ANALOG DEVICES INC) LC2MOS Signal Conditioning ADC PDF資料下載
參數資料
| 型號： | AD7712AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Signal Conditioning ADC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數： | 6/28頁 |
| 文件大小： | 229K |
| 代理商： | AD7712AN |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
REV. E
–6–
AD7712
Limit at T
MIN
, T
MAX
(A, S Versions)
Parameter
Units
Conditions/Comments
External Clocking Mode
f
SCLK
t
20
t
21
t
22
t
t
23
t
257
f
CLK IN
/5
0
0
2
×
t
CLK IN
0
4
×
t
CLK IN
10
2
×
t
CLK IN
+ 20
2
×
t
CLK IN
2
×
t
CLK IN
t
CLK IN
+ 10
10
t
CLK IN
+ 10
10
5
×
t
CLK IN
/2 + 50
0
0
4
×
t
CLK IN
2
×
t
CLK IN
– SCLK High
30
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Serial Clock Input Frequency
DRDY
to
RFS
Setup Time
DRDY
to
RFS
Hold Time
A0 to
RFS
Setup Time
A0 to
RFS
Hold Time
Data Access Time (
RFS
Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
t
26
t
27
t
t
28
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Falling Edge to
DRDY
High
SCLK to Data Valid Hold Time
t
t
30
t
32
t
33
t
34
t
35
t
36
RFS
/
TFS
to SCLK Falling Edge Hold Time
RFS
to Data Valid Hold Time
A0 to
TFS
Setup Time
A0 to
TFS
Hold Time
SCLK Falling Edge to
TFS
Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
NOTES
1
Guaranteed by design, not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input
signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 11 to 14.
3
The AD7712 is specified with a 10 MHz clock for AV
DD
voltages of +5 V
±
5%. It is specified with an 8 MHz clock for AV
DD
voltages greater than 5.25 V and less
than 10.5 V.
4
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7712 is not in STANDBY mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.
5
The AD7712 is production tested with f
CLK IN
at 10 MHz (8 MHz for AV
DD
< +5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6
Specified using 10% and 90% points on waveform of interest.
7
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
8
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are
the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
Specifications subject to change without notice.
TO OUTPUT
PIN
+2.1V
1.6mA
200
m
A
100pF
Figure 1. Load Circuit for Access Time and Bus Relinquish
Time
PIN CONFIGURATION
DIP AND SOIC
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7712
AV
DD
V
SS
TP
STANDBY
AIN1(–)
MCLK IN
MCLK OUT
A0
AIN1(+)
MODE
SCLK
SYNC
V
BIAS
REF IN(–)
REF IN(+)
REF OUT
AIN2
DGND
DV
DD
SDATA
DRDY
AGND
TFS
RFS
相關PDF資料 |
PDF描述 |
|---|---|
| AD7712AQ | LC2MOS Signal Conditioning ADC |
| AD7712AR | LC2MOS Signal Conditioning ADC |
| AD7712SQ | LC2MOS Signal Conditioning ADC |
| AD7712* | Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C |
| AD7712 | Signal Conditioning ADC(LC2MOS信號調節A/D轉換器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7712ANZ | 功能描述:IC ADC SIGNAL COND LC2MOS 24-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7712ANZ | 制造商:Analog Devices 功能描述:IC ADC 24-BIT SIGMA DELTA |
| AD7712AQ | 制造商:Rochester Electronics LLC 功能描述:24 BIT SIGMA DELTA ADC IC - Bulk |
| AD7712AR | 功能描述:IC ADC SIGNAL COND LC2MOS 24SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD7712AR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 1.028ksps 24-bit Serial 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 1.028KSPS 24BIT SERL 24SOIC W - Tape and Reel |
發布緊急采購，3分鐘左右您將得到回復。