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參數資料
| 型號： | AD7712AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Signal Conditioning ADC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 26/28頁 |
| 文件大小： | 229K |
| 代理商： | AD7712AR |
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REV. E
–26–
AD7712
Table VIII. 8XC51 Code for Writing to the AD7712
MOV SCON,#00000000B;
Configure 8051 for MODE 0
Operation & Enable Serial Reception
Enable Transmit Interrupt
Prioritize the Transmit Interrupt
Bring
TFS
High
Bring
RFS
High
Sets Number of Bytes to Be Written
in a Write Operation
Start Address in RAM for Bytes
Clear Accumulator
Initialize the Serial Port
MOV IE,#10010000B;
MOV IP,#00010000B;
SETB 91H;
SETB 90H;
MOV R1,#003H;
MOV R0,#030H;
MOV A,#00H;
MOV SBUF,A;
WAIT:
JMP WAIT;
INT ROUTINE:
NOP;
MOV A,R1;
JZ FIN;
DEC R1;
MOV A,@R;
INC R0;
RLC A;
Wait for Interrupt
Interrupt Subroutine
Load R1 to Accumulator
If Zero Jump to FIN
Decrement R1 Byte Counter
Move Byte into the Accumulator
Increment Address
Rearrange Data—From LSB First
to MSB First
MOV B.0,C; RLC A; MOV B.1,C; RLC A;
MOV B.2,C; RLC A; MOV B.3,C; RLC A;
MOV B.4,C; RLC A; MOV B.5,C; RLC A;
MOV B.6,C; RLC A: MOV B.7,C; MOV A,B;
CLR 93H;
CLR 91H;
MOV SBUF,A;
RETI;
FIN:
SETB 91H;
SETB 93H;
RETI;
Bring A0 Low
Bring
TFS
Low
Write to Serial Port
Return from Subroutine
Set
TFS
High
Set A0 High
Return from Interrupt Subroutine
AD7712 to 68HC11 Interface
Figure 19 shows an interface between the AD7712 and the
68HC11 microcontroller. The AD7712 is configured for its
external clocking mode while the SPI port is used on the
68HC11 which is in its single chip mode. The
DRDY
line from
the AD7712 is connected to the Port PC0 input of the 68HC11
so the
DRDY
line is polled by the 68HC11. The
DRDY
line
can be connected to the
IRQ
input of the 68HC11 if an inter-
rupt driven system is preferred. The 68HC11 MOSI and MISO
lines should be configured for wired-or operation. Depending
on the interface configuration, it may be necessary to provide
bidirectional buffers between the 68HC11’s MOSI and MISO
lines.
The 68HC11 is configured in the master mode with its CPOL
bit set to a logic zero and its CPHA bit set to a logic one. With a
10 MHz master clock on the AD7712, the interface will operate
with all four serial clock rates of the 68HC11.
AD7712
SCLK
SDATA
A0
RFS
TFS
PC0
MISO
SCK
PC1
PC2
MODE
PC3
DRDY
SYNC
68HC11
MOSI
SS
DV
DD
DV
DD
Figure 19. AD7712 to 68HC11 Interface
AD7712 to ADSP-2105 Interface
An interface circuit between the AD7712 and the ADSP-2105
microprocessor is shown in Figure 20. In this interface, the
AD7712 is configured for its self-clocking mode while the
RFS
and
TFS
pins of the ADSP-2105 are configured as inputs and
the ADSP-2105 serial clock line is also configured as an input.
When the ADSP-2105’s serial clock is configured as an input it
needs a couple of clock pulses to initialize itself correctly before
accepting data. Therefore, the first read from the AD7712 may
not read correct data. In the interface shown, a read operation
to the AD7712 accesses either the output register or the calibra-
tion registers. Data cannot be read from the control register. A
write operation always writes to the control or calibration
registers.
DRDY
is used as the frame synchronization pulse for read op-
erations from the output register and it is decoded with A0 to
drive the
RFS
inputs of both the AD7712 and the ADSP-2105.
The latched A0 line drives the
TFS
inputs of both the AD7712
and the ADSP-2105 as well as the AD7712 A0 input.
AD7712
SDATA
SCLK
A0
RFS
TFS
DR
SCLK
MODE
A0
DRDY
ADSP-2105
DT
DMWR
TFS
RFS
DV
DD
D
74HC74
Q
Q
Figure 20. AD7712 to ADSP-2105 Interface
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