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參數資料
| 型號： | AD7712EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC 2 MOS Signal Conditioning ADC(229.08 k) |
| 中文描述： | 立法會二馬鞍山信號調理模數轉換器（229.08十一） |
| 文件頁數： | 22/28頁 |
| 文件大小： | 229K |
| 代理商： | AD7712EB |
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REV. E
–22–
AD7712
Figure 13a shows a read operation from the AD7712 where
RFS
remains low for the duration of the data word transmission.
With
DRDY
low, the
RFS
input is brought low. The input
SCLK signal should be low between read and write operations.
RFS
going low places the MSB of the word to be read on the
serial data line. All subsequent data bits are clocked out on a
high to low transition of the serial clock and are valid prior to
the following rising edge of this clock. The penultimate falling
edge of SCLK clocks out the LSB and the final falling edge
resets the
DRDY
line high. This rising edge of
DRDY
turns off
the serial data output.
Figure 13b shows a timing diagram for a read operation where
RFS
returns high during the transmission of the word and re-
turns low again to access the rest of the data word. Timing
parameters and functions are very similar to that outlined for
Figure 13a, but Figure 13b has a number of additional times to
show timing relationships when
RFS
returns high in the middle
of transferring a word.
RFS
should return high during a low time of SCLK. On the
rising edge of
RFS
, the SDATA output is turned off.
DRDY
remains low and will remain low until all bits of the data word
are read from the AD7712, regardless of the number of times
RFS
changes state during the read operation. Depending on the
time between the falling edge of SCLK and the rising edge of
RFS
, the next bit (BIT N + 1) may appear on the databus be-
fore
RFS
goes high. When
RFS
returns low again, it activates
the SDATA output. When the entire word is transmitted, the
DRDY
line will go high, turning off the SDATA output as per
Figure 13a.
RFS
(I)
SCLK (I)
SDATA (O)
LSB
MSB
THREE-STATE
A0 (I)
DRDY
(O)
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
Figure 13a. External Clocking Mode, Output Data Read Operation
THREE-STATE
MSB
BIT N
BIT N+1
SDATA (O)
SCLK (I)
RFS
(I)
A0 (I)
DRDY
(O)
t
20
t
22
t
26
t
24
t
25
t
27
t
31
t
24
t
25
t
30
Figure 13b. External Clocking Mode, Output Data Read Operation (
RFS
Returns High During Read Operation)
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| AD7713ANZ | 功能描述:IC ADC 24BIT SIGMA-DELTA 24-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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