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參數(shù)資料
| 型號： | AD7713AQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Loop-Powered Signal Conditioning ADC |
| 中文描述： | 3-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 516K |
| 代理商： | AD7713AQ |
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2
–5–
REV. C
AD7713
Limit at T
MIN
, T
MAX
(A, S Versions)
Parameter
Units
Conditions/Comments
External-Clocking Mode
f
SCLK
t
20
t
21
t
22
t
23
t
246
t
256
f
CLK IN
/5
0
0
2
×
t
CLK IN
0
4
×
t
CLK IN
10
2
×
t
CLK IN
+ 20
2
×
t
CLK IN
2
×
t
CLK IN
t
CLK IN
+ 10
10
t
CLK IN
+ 10
10
5
×
t
CLK IN
/2 + 50
0
0
4
×
t
CLK IN
2
×
t
CLK IN
– SCLK High
30
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Serial Clock Input Frequency
DRDY
to
RFS
Setup Time
DRDY
to
RFS
Hold Time
A0 to
RFS
Setup Time
A0 to
RFS
Hold Time
Data Access Time (
RFS
Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
t
26
t
27
t
28
t
297
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Falling Edge to
DRDY
High
SCLK to Data Valid Hold Time
t
30
t
317
t
32
t
33
t
34
t
35
t
36
RFS
/
TFS
to SCLK Falling Edge Hold Time
RFS
to Data Valid Hold Time
A0 to
TFS
Setup Time
A0 to
TFS
Hold Time
SCLK Falling Edge to
TFS
Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
NOTES
1
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 10 to 13.
3
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in STANDBY mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.
4
The AD7713 is production tested with f
CLK IN
at 2 MHz. It is guaranteed by characterization to operate at 400 kHz.
5
Specified using 10% and 90% points on waveform of interest.
6
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
7
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are
the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
TO OUTPUT
PIN
+2.1V
1.6mA
200μA
100pF
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
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