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參數(shù)資料
| 型號(hào)： | AD7713AR |
| 廠(chǎng)商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | LC2MOS Loop-Powered Signal Conditioning ADC |
| 中文描述： | 3-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁(yè)數(shù)： | 7/28頁(yè) |
| 文件大小： | 516K |
| 代理商： | AD7713AR |
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2
–7–
REV. C
AD7713
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
1
SCLK
Serial Clock. Logic input/output depending on the status of the MODE pin. When MODE is high, the
device is in its self-clocking mode and the SCLK pin provides a serial clock output. This SCLK becomes
active when
RFS
or
TFS
goes low and it goes high impedance when either
RFS
or
TFS
returns high or when
the device has completed transmission of an output word. When MODE is low, the device is in its external
clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to the AD7713 in smaller batches of data.
Master Clock signal for the device. This can be provided in the form of a crystal or external clock. A crystal can
be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a
CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 2 MHz.
When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.
Address Input. With this input low, reading and writing to the device is to the control register. With this nput
high, access is to either the data register or the calibration registers.
Logic Input which allows for synchronization of the digital filters when using a number of AD7713s. It resets
the nodes of the digital filter.
Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its
external clocking mode.
Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input
is connected to an output current source which can be used to check that an external transducer has burnt out
or gone open circuit. This output current source can be turned on/off via the control register.
Analog Input Channel 1. Negative input of the programmable gain differential analog input.
Analog Input Channel 2. Positive input of the programmable gain differential analog input.
Analog Input Channel 2. Negative input of the programmable gain differential analog input.
Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power
consumption to less than 50
μ
W.
Analog Positive Supply Voltage, +5 V to +10 V.
Constant Current Output. A nominal 200
μ
A constant current is provided at this pin and this can be used
as the excitation current for RTDs. This, current can be turned on or off via the control register.
Reference Input. The REF IN(–) can lie anywhere between AV
DD
and AGND provided REF IN(+) is
greater than REF IN(–).
Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).
REF IN(+) can lie anywhere between AV
DD
and AGND.
Constant Current Output. A nominal 200
μ
A constant current is provided at this pin and this can be used
as the excitation current for RTDs. This, current can be turned on or off via the control register. This
second current can be used to eliminate lead resistanced errors in three-wire RTD configurations.
Analog Input Channel 3. High level analog input which accepts an analog input voltage range of
4
×
V
REF
/GAIN. At the nominal V
REF
of +2.5 V and a gain of 1, the AIN3 input voltage range is
0 to
±
10 V.
Ground Reference Point for Analog Circuitry.
Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial
data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active
after
TFS
goes low. In the external clocking mode,
TFS
must go low before the first bit of the data word
is written to the part.
Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the
self-clocking mode, the SCLK and SDATA lines both become active after
RFS
goes low. In the external
clocking mode, the SDATA line becomes active after
RFS
goes low.
2
MCLK IN
3
4
MCLK OUT
A0
5
SYNC
6
MODE
7
AIN1(+)
8
9
AIN1(–)
AIN2(+)
AIN2(–)
STANDBY
10
11
12
13
AV
DD
RTD1
14
REF IN(–)
15
REF IN(+)
16
RTD2
17
AIN3
18
19
AGND
TFS
20
RFS
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|---|---|
| AD7713AR-REEL | 制造商:Analog Devices 功能描述:24-BIT SIGMA DELTA ADC IC - Tape and Reel |
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| AD7713ARZ | 功能描述:IC ADC SIGNAL COND LC2MOS 24SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類(lèi)型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱(chēng):497-5435-6 |
| AD7713ARZ | 制造商:Analog Devices 功能描述:IC ADC 24-BIT SIGMA DELTA |
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