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參數資料
| 型號： | AD7714 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Signal Conditioning ADC(信號調節A/D轉換器) |
| 中文描述： | 信號調理模數轉換器（信號調節的A / D轉換器） |
| 文件頁數： | 26/40頁 |
| 文件大小： | 321K |
| 代理商： | AD7714 |
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AD7714
REV. C
–26–
Power-Up and Calibration
On power-up, the AD7714 performs an internal reset which sets
the contents of the internal registers to a known state. There
are default values loaded to all registers after a power-on or
reset. The default values contain nominal calibration coefficients
for the calibration registers. However, to ensure correct calibra-
tion for the device a calibration routine should be performed
after power-up.
The power dissipation and temperature drift of the AD7714 are
low and no warm-up time is required before the initial calibra-
tion is performed. However, if an external reference is being
used, this reference must have stabilized before calibration is
initiated. Similarly, if the clock source for the part is generated
from a crystal or resonator across the MCLK pins, the start-up
time for the oscillator circuit should elapse before a calibration
is initiated on the part (see below).
USING THE AD7714
Clocking and Oscillator Circuit
The AD7714 requires a master clock input, which may be an
external CMOS compatible clock signal applied to the MCLKIN
pin with the MCLKOUT pin left unconnected. Alternatively, a
crystal or ceramic resonator of the correct frequency can be
connected between MCLKIN and MCLKOUT in which case
the clock circuit will function as an oscillator, providing the
clock source for the part. The input sampling frequency, the
modulator sampling frequency, the –3dB frequency, output
update rate and calibration time are all directly related to the
master clock frequency, f
CLKIN
. Reducing the master clock
frequency by a factor of 2 will halve the above frequencies and
update rate and double the calibration time. The current drawn
from the DV
DD
power supply is also directly related to f
CLKIN
.
Reducing f
CLKIN
by a factor of 2 will halve the DV
DD
current
but will not affect the current drawn from the AV
DD
power supply.
Using the part with a crystal or ceramic resonator between the
MCLK IN and MCLK OUT pins generally causes more cur-
rent to be drawn from DV
DD
than when the part is clocked from
a driven clock signal at the MCLK IN pin. This is because the
on-chip oscillator circuit is active in the case of the crystal or
ceramic resonator. Therefore, the lowest possible current on
the AD7714 is achieved with an externally applied clock at the
MCLK IN pin with MCLK OUT unconnected and unloaded.
The amount of additional current taken by the oscillator
depends on a number of factors—first, the larger the value of
capacitor placed on the MCLKIN and MCLKOUT pins, then
the larger the DV
DD
current consumption on the AD7714. Care
should be taken not to exceed the capacitor values recommended
by the crystal and ceramic resonator manufacturers to avoid
consuming unnecessary DV
DD
current. Typical values recom-
mended by crystal or ceramic resonator manufacturers are in the
range of 30pF to 50pF and if the capacitor values on MCLK
IN and MCLK OUT are kept in this range they will not result
in any excessive DV
DD
current. Another factor that influences
the DV
DD
current is the effective series resistance (ESR) of the
crystal which appears between the MCLK IN and MCLK OUT
pins of the AD7714. As a general rule, the lower the ESR value
then the lower the current taken by the oscillator circuit.
When operating with a clock frequency of 2.4576MHz, there is
no appreciable difference in the DV
DD
current between an
externally applied clock and a crystal resonator when operating
with a DV
DD
of +3V. With DV
DD
= +5V and f
CLK IN
=
2.4576MHz, the typical DV
DD
current increases by 50
μ
A for a
crystal/resonator supplied clock versus an externally applied
clock. The ESR values for crystals and resonators at this fre-
quency tend to be low and as a result there tends to be little
difference between different crystal and resonator types.
When operating with a clock frequency of 1MHz, the ESR
value for different crystal types varies significantly. As a result,
the DV
DD
current drain varies across crystal types. When using
a crystal with an ESR of 700
or when using a ceramic resona-
tor, the increase in the typical DV
DD
current over an externally-
applied clock is 50
μ
A with DV
DD
= +3V and 175
μ
A with
DV
DD
= +5V. When using a crystal with an ESR of 3k
, the
increase in the typical DV
DD
current over an externally applied
clock is again 50
μ
A with DV
DD
= +3V but 300
μ
A with
DV
DD
= +5V.
The on-chip oscillator circuit also has a start-up time associated
with it before it is oscillating at its correct frequency and correct
voltage levels. The typical start up time for the circuit is 10ms
with a DV
DD
of +5V and 15ms with a DV
DD
of +3V. At 3V
supplies, depending on the loading capacitances on the MCLK
pins, a 1M
feedback resistor may be required across the crys-
tal or resonator in order to keep the start up times around the
15ms duration.
The AD7714’s master clock appears on the MCLK OUT pin of
the device. The maximum recommended load on this pin is one
CMOS load. When using a crystal or ceramic resonator to gen-
erate the AD7714’s clock, it may be desirable to then use this
clock as the clock source for the system. In this case, it is recom-
mended that the MCLK OUT signal is buffered with a CMOS
buffer before being applied to the rest of the circuit.
System Synchronization
The
SYNC
input (or FSYNC bit) allows the user to reset the
modulator and digital filter without affecting any of the setup
conditions on the part. This allows the user to start gathering
samples of the analog input from a known point in time, i.e., the
rising edge of
SYNC
or when a 1 is written to FSYNC.
The
SYNC
input can also be used to allow two other functions.
If multiple AD7714s are operated from a common master clock,
they can be synchronized to update their output registers simul-
taneously. A falling edge on the
SYNC
input (or a 1 written to
the FSYNC bit of the Mode Register) resets the digital filter and
analog modulator and places the AD7714 into a consistent,
known state. While the
SYNC
input is low (or FSYNC high),
the AD7714 will be maintained in this state. On the rising edge
of
SYNC
(or when a 0 is written to the FSYNC bit), the modu-
lator and filter are taken out of this reset state and on the next
clock edge the part starts to gather input samples again. In a
system using multiple AD7714s, a common signal to their
SYNC
inputs will synchronize their operation. This would nor-
mally be done after each AD7714 has performed its own cali-
bration or has had calibration coefficients loaded to it. The
output updates will then be synchronized with the maximum
possible difference between the output updates of the individual
AD7714s being one MCLK IN cycle.
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