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參數資料
型號: AD7714AN-3
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: VARISTOR 30VRMS 0805 SMD
中文描述: 5-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24
封裝: 0.300 INCH, PLASTIC, DIP-24
文件頁數: 11/40頁
文件大小: 306K
代理商: AD7714AN-3
2
AD7714
REV. C
–11–
AD7714-5 OUTPUT NOISE
Table Ia shows the output rms noise and effective resolution for some typical notch and –3dB frequencies for the AD7714-5 with
f
CLKIN
= 2.4576MHz while Table Ib gives the information for f
CLK IN
= 1MHz. The numbers given are for the bipolar input ranges
with a V
REF
of +2.5V and with BUFFER = 0. These numbers are typical and are generated at an analog input voltage of 0V. The
numbers in brackets in each table are for the effective resolution of the part (rounded to the nearest 0.5LSB). The effective resolu-
tion of the device is defined as the ratio of the output rms noise to the input full scale (i.e.,
2 ×
V
REF
/GAIN
).
It should be noted that
it is not calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms numbers
while effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms noise as
quoted in the tables.
The output noise from the part comes from two sources. The first is the electrical noise in the semiconductor devices used in the
implementation of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quan-
tization noise is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at
an even lower level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter
notch settings (below 100Hz approximately for f
CLK IN
= 2.4576MHz and below 40Hz approximately for f
CLK IN
= 1MHz) tend to
be device noise dominated while higher notch settings are dominated by quantization noise. Changing the filter notch and cutoff
frequency in the quantization-noise dominated region results in a more dramatic improvement in noise performance than it does in
the device-noise dominated region as shown in Table I. Furthermore, quantization noise is added after the PGA, so effective resolu-
tion is largely independent of gain for the higher filter notch frequencies. Meanwhile, device noise is added in the PGA and, there-
fore, effective resolution reduces at high gains for lower notch frequencies. Additionally, in the device-noise dominated region, the
output noise (in
μ
V) is largely independent of reference voltage while in the quantization-noise dominated region, the noise is pro-
portional to the value of the reference. It is possible to do post-filtering on the device to improve the output data rate for a given
–3dB frequency and also to further reduce the output noise.
At the lower filter notch settings (below 60Hz for f
CLK IN
= 2.4576MHz and below 25Hz for f
CLK IN
= 1MHz), the no missing
codes performance of the device is at the 24-bit level. At the higher settings, more codes will be missed until at 1kHz notch setting
for f
CLKIN
= 2.4576MHz (400Hz for f
CLK IN
= 1MHz), no missing codes performance is only guaranteed to the 12-bit level.
Table Ia. AD7714-5 Output Noise/Resolution vs. Gain and First Notch for f
CLK IN
= 2.4576MHz, BUFFER = 0
Filter First
Notch & O/P
Data Rate
Typical Output RMS Noise in
m
V (Effective Resolution in Bits)
Gain of
Gain of
Gain of
2
4
8
–3dB
Frequency
Gain of
Gain of
16
Gain of
32
Gain of
64
Gain of
128
1
5Hz
10Hz
25Hz
30Hz
50Hz
60Hz
100Hz
250Hz
500Hz
1kHz
1.31Hz
2.62Hz
6.55Hz
7.86Hz
13.1Hz
15.72Hz
26.2Hz
65.5Hz
131Hz
262Hz
0.87
1.0
1.8
2.5
4.33
5.28
12.1
127
533
2,850 (11)
(22.5)
(22.5)
(21.5)
(21)
(20)
(20)
(18.5)
(15.5)
(13)
0.48
0.78
1.1
1.31
2.06
2.36
5.9
58
267
1,258 (11)
(22.5)
(21.5)
(21)
(21)
(20)
(20)
(18.5)
(15.5)
(13)
0.24 (22.5)
0.48 (21.5)
0.63 (21)
0.84 (20.5)
1.2
(20)
1.33 (20)
2.86 (19)
29
(15.5)
137 (13)
680 (11)
0.2
0.33 (21)
0.5
0.57 (20)
0.64 (20)
0.87 (19.5) 0.63 (19)
1.91 (18.5) 1.06 (18)
15.9 (15.5) 6.7
66
(13)
297 (11)
(21.5) 0.18 (20.5) 0.17 (20)
0.25 (20.5) 0.25 (19.5) 0.25 (18.5) 0.25 (17.5)
(20)
0.44 (19.5) 0.41 (18.5) 0.38 (17.5) 0.38 (16.5)
0.46 (19.5) 0.43 (18.5) 0.4
0.54 (19)
0.46 (18.5) 0.46 (17.5) 0.46 (16.5)
0.62 (18)
0.83 (17.5) 0.82 (16.5) 0.76 (15.5)
(15.5) 3.72 (15.5) 1.96 (15.5) 1.5
38
(13)
20
(13)
131 (11)
99
(10.5) 53
0.17 (19)
0.17 (18)
(17.5) 0.4
(16.5)
0.6
(17)
0.56 (16)
(14.5)
(13)
(10.5)
8.6
(13)
(10.5) 28
4.4
Table Ib. AD7714-5 Output Noise/Resolution vs. Gain and First Notch for f
CLK IN
= 1MHz, BUFFER = 0
Filter First
Notch & O/P
Data Rate
Typical Output RMS Noise in
m
V (Effective Resolution in Bits)
Gain of
Gain of
Gain of
2
4
8
–3dB
Frequency
Gain of
Gain of
16
Gain of
32
Gain of
64
Gain of
128
1
2Hz
4Hz
10Hz
25 Hz
30Hz
50Hz
60Hz
100Hz
200Hz
400Hz
0.52Hz
1.05Hz
2.62Hz
6.55Hz
7.86Hz
13.1Hz
15.72Hz
26.2Hz
52.4Hz
104.8Hz
0.75
1.04
1.66
5.2
7.1
19.4
25
102
637
2,830 (11)
(22.5)
(22)
(21.5)
(20)
(19.5)
(18)
(17.5)
(15.5)
(13)
0.56
0.88
1.01
2.06
3.28
9.11
16
58
259
1,430 (11)
(22)
(21.5)
(21.5)
(20)
(19.5)
(18)
(17.5)
(15.5)
(13)
0.31 (22)
0.45 (21.5)
0.77 (20.5)
1.4
(20)
1.42 (19.5)
4.2
(18)
6.5
(17.5)
25
(15.5)
130 (13)
720 (11)
0.19 (21.5) 0.17 (21)
0.28 (21)
0.41 (20.5) 0.37 (19.5) 0.35 (19)
0.86 (19.5) 0.63 (19)
1.07 (19)
0.78 (18.5) 0.64 (18)
2.45 (18)
1.56 (17.5) 1.1
2.9
(17.5) 1.93 (17.5) 1.4
13.5 (15.5) 5.7
76
(13)
33
334 (11)
220 (10.5) 94
0.14 (20)
0.14 (19)
0.14 (18)
0.21 (20.5) 0.21 (19.5) 0.21 (18.5) 0.21 (17.5)
0.35 (18)
0.59 (17)
0.61 (17)
0.82 (16.5) 0.8
1.1
(16)
(15.5) 2.1
(13)
11
(10.5) 54
0.35 (17)
0.59 (16)
0.61 (16)
0.61 (18)
(17)
(17)
(15.5)
0.98 (15.5)
1.3
(15)
6
(12.5)
(10.5)
(15.5) 3.9
(13)
(15)
(13)
(10.5) 25
16
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相關代理商/技術參數
參數描述
AD7714AN5 制造商:ANA 功能描述:24 BIT, 1KSPS, DIP 24
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AD7714ANZ-5 功能描述:IC ADC SIGNAL COND 5V 24-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數:8 采樣率(每秒):1M 數據接口:串行,SPI? 轉換器數目:1 功率耗散(最大):- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤(4x4) 包裝:Digi-Reel® 輸入數目和類型:8 個單端,單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6
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